RTL Development — Complete Guide

// ✓ GOOD: Proper sequential + combinational separation
module good_rtl #(parameter W=8)(
  input  wire         clk, rst_n, en,
  input  wire [W-1:0] d,
  output reg  [W-1:0] q
);
  // Sequential block: use <= always
  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) q <= '0;        // async reset — clear on negedge rst_n
    else if (en) q <= d;         // clock enable — power-friendly clock gating
  end
endmodule

// ✗ BAD: Mixed blocking/non-blocking in sequential — DO NOT DO THIS
always @(posedge clk) begin
  a = b + c;    // blocking: a is evaluated immediately (like software)
  d <= a;        // non-blocking: d gets the OLD value of a, not the new one!
  // Bug: simulation says d gets new a, synthesis gives different result
end

// ✓ GOOD: Combinational with full case coverage (no latch)
always @(*) begin
  case (op)
    2'b00: out = a + b;
    2'b01: out = a - b;
    2'b10: out = a & b;
    default: out = '0;    // MUST have default — otherwise latch inferred!
  endcase
end

// ✗ BAD: Missing else → LATCH INFERRED (synthesis warning)
always @(*) begin
  if (en) out = data;    // if en=0, what is out? → latch holds old value
  // Fix: add else out = '0;
end

// ✓ GOOD: FSM — 3-block style (state register + next-state + output)
typedef enum logic [1:0] {IDLE, BUSY, DONE} state_t;
state_t curr_state, next_state;

// Block 1: state register
always @(posedge clk or negedge rst_n)
  if (!rst_n) curr_state <= IDLE;
  else        curr_state <= next_state;

// Block 2: next-state logic (combinational)
always @(*) begin
  next_state = curr_state;           // default: stay in current state
  case (curr_state)
    IDLE: if (start) next_state = BUSY;
    BUSY: if (done_flag) next_state = DONE;
    DONE: next_state = IDLE;
    default: next_state = IDLE;
  endcase
end

// Block 3: output logic (Moore — based on state only)
always @(*) begin
  busy_out = (curr_state == BUSY);
  valid_out = (curr_state == DONE);
end

// ✓ Clock Gating — most impactful RTL power technique
// Instead of: always @(posedge clk) if (en) q <= d;
// Infer ICG (Integrated Clock Gate) explicitly:
module icg_example(
  input  wire clk, en,
  input  wire [7:0] d,
  output reg  [7:0] q
);
  wire gated_clk;
  // Synthesis tool infers ICG cell from this pattern
  // ICG: latch enable on level, AND with clock
  CLKGATE_CELL icg (.CLK(clk), .EN(en), .GCLK(gated_clk));
  always @(posedge gated_clk) q <= d;  // only toggles when en=1
endmodule

// ✓ Operand Isolation — prevent glitching through inactive datapaths
// Without isolation: even when unit is off, operands toggle the adder
// With isolation: clamp inputs to 0 when unit disabled
assign add_a_iso = unit_en ? a : '0;
assign add_b_iso = unit_en ? b : '0;
assign result = add_a_iso + add_b_iso;  // no glitch power when unit_en=0

// ✓ One-Hot encoding for FSM — faster decode, lower glitch switching
// vs binary encoding (smaller state register, more decode logic)
// One-hot: only 1 bit changes per transition → lower switching activity
typedef enum logic [3:0] {
  S_IDLE = 4'b0001,
  S_READ = 4'b0010,
  S_PROC = 4'b0100,
  S_DONE = 4'b1000
} state_t;  // synthesis attribute: (* fsm_encoding = "one_hot" *)