Tutorial Series · 15 Topics

Verilog HDL Tutorial Series

Learn Verilog from scratch — from your very first module to synthesizable RTL design patterns. Every topic has working code examples, circuit diagrams, and clear explanations for both students and working engineers.

15 step-by-step tutorials Runnable code in every lesson Diagrams & waveforms Interview-ready examples Synthesis-safe patterns

All Tutorials

Start from the Beginning

Each tutorial builds on the previous one. Start at Tutorial 1 if you're new to Verilog, or jump to any topic you need.

Introduction to Verilog HDL

What Verilog is, hardware vs software mindset, concurrency, levels of abstraction (behavioral/RTL/gate), and your first Verilog module.

What is VerilogConcurrencyFirst Module

Capstone Project: UART + FIFO

Build a complete UART receiver connected to a synchronous FIFO. Write a self-checking testbench, simulate with Icarus Verilog, and view waveforms in GTKWave.

UART RX FSM Sync FIFO Testbench Integration Icarus Verilog

RTL Design Patterns

Production RTL patterns: pipeline stages, valid-ready handshake, synchronous FIFO with MSB pointer trick, round-robin arbiter, clock enable vs clock gating, 2-FF CDC synchronizer, skid buffer.

pipelinevalid-readyFIFOCDC

Finite State Machines (FSM)

Design Moore and Mealy FSMs in Verilog: binary vs one-hot encoding, the 3-always coding pattern, traffic light controller, 101 sequence detector, and UART receiver FSM.

Moore/Mealyone-hot3-alwaysUART

Gate-Level Modeling

Use Verilog built-in primitives (and/or/not/nand/nor/xor/buf/bufif1), model gate delays with rise/fall/turn-off times, build netlists, and understand post-synthesis simulation.

and/or/notbufif1gate delayUDP

System Tasks & Functions

Complete guide to $display, $monitor, $strobe, $time, $random, $readmemh, $dumpfile, $clog2, $signed — every simulator built-in with format specifiers and real examples.

$display$monitor$random$clog2

Tasks & Functions

Write reusable Verilog code blocks: task vs function differences, the automatic keyword for safe concurrent calls and recursion, RTL tasks, and testbench bus-transaction examples.

taskfunctionautomaticdisable

Testbench Writing

Write self-checking testbenches: clock generation, reset sequences, stimulus methods, $display/$monitor/$error, VCD waveform dump, and simulate with Icarus Verilog + GTKWave.

testbench$displayVCDIcarus Verilog

Parameters & generate

Make modules configurable with parameter/localparam. Use generate-for to replicate N hardware instances, generate-if for conditional architectures. N-bit adder and RAM examples.

parameterlocalparamgenerate-forgenvar

if, case, casex Statements

if-else chains → priority mux trees. case → parallel mux. casez wildcards. Latch-free patterns, full_case/parallel_case directives, and FSM output decode examples.

if / elsecase / defaultcasezPriority vs Parallel

Blocking vs Non-Blocking

The = vs <= rule: why blocking causes race conditions in clocked blocks, how the NBA event queue works, shift register bug example, and the golden rule for RTL design.

= vs <=Race ConditionNBA QueueShift Register Bug

always & assign Blocks

Continuous assign vs combinational always @(*) vs sequential always @(posedge clk). Sensitivity lists, async/sync reset, latch inference, and the blocking vs non-blocking rule.

assignalways @(*)posedge clkLatch-free RTL

Operators in Verilog

Arithmetic, bitwise, logical, reduction, shift, conditional (?:), concatenation ({}) and replication operators — each mapped to real hardware with working examples.

ArithmeticBitwiseReductionShiftMux (?:)

Data Types in Verilog

wire, reg, integer, real, time, parameter, localparam — the 4-value logic system (0, 1, X, Z), vectors, arrays, and signed vs unsigned arithmetic.

wire / reg4-value logicparameterVectors

Module & Port Declaration

Declare modules, define input/output/inout ports, set bit-widths, understand wire vs reg on ports, ANSI vs legacy style, and instantiate modules hierarchically.

module / endmoduleinput output inoutPort WidthInstantiation