What is setup time in a flip-flop?

Setup time (Tsu) is the minimum time data must be stable at the flip-flop input BEFORE the active clock edge arrives. If this window is violated, the internal latch may fail to resolve to a valid logic level, causing metastability or wrong data capture.

What is a hold time violation and how is it fixed?

A hold violation occurs when data changes too soon AFTER the clock edge — faster than the hold requirement. It is caused by very short combinational paths between flip-flops. Hold violations cannot be fixed by reducing the clock frequency; the only fix is inserting delay buffers on the data path or optimizing the clock tree.

What is setup slack and hold slack?

Setup slack = (T_period + T_skew - T_jitter) - (T_cq + T_comb + T_setup). Positive slack means the path meets timing. Hold slack = (T_cq + T_comb_min) - (T_hold + T_skew). Both must be positive (or zero) for a timing-clean design.

What is OCV in Static Timing Analysis?

On-Chip Variation (OCV) accounts for transistors on the same die behaving differently due to local manufacturing variations. STA tools apply derating factors — slowing the data path and speeding the clock path (for setup) or vice versa (for hold) to find the absolute worst-case slack.

Common Path Pessimism Removal (CPPR) removes the impossible pessimism added by OCV on clock tree segments shared by both the launch and capture paths. Since a shared buffer cannot simultaneously be fast and slow, CPPR adds back the removed margin on the common portion, giving a more realistic (but still safe) slack value.

Setup & Hold Time – Static Timing Analysis Deep Dive

Section 01

The Physics of Sequential Stability

A flip-flop is not an instantaneous switch — it is a regenerative feedback loop built from MOSFET transistors. When a clock edge arrives, the internal master latch begins to "lock" the value on its input by moving charge across parasitic capacitances. This process takes time. If the input voltage changes exactly as the clock is transitioning, the feedback loop may enter an equilibrium between the 0 and 1 voltage rails — the metastable state.

Two timing parameters guard this process: Setup time (T_su) — how long before the clock edge the data must be stable — and Hold time (T_h) — how long after the clock edge the data must remain stable. Together they define the timing aperture: the forbidden zone during which data must not change.

The aperture time = Tsu + Th. During this window, data changing at the flip-flop input is guaranteed to produce incorrect or metastable output.

Section 02

Setup Time (T_su) — Pre-Clock Stability

Setup time is the minimum duration data must be stable at the flip-flop D input before the active clock edge. It exists because the master latch inside the flip-flop needs time to charge its internal capacitances to a voltage above the switching threshold of the slave latch.

What happens on a Setup violation?

The master latch hasn't fully resolved when the slave latch opens. The output Q may sample old data, new data, or enter a metastable intermediate level — all of which produce a logic error.

How is Setup violation fixed?

Reduce the combinational logic delay between registers (pipelining, gate sizing, logic restructuring), reduce clock frequency, or add a faster cell library corner.

Setup check: T_launch_clk + T_cq + T_comb + T_su <= T_capture_clk + T_period

Setup Slack = (T_period + T_skew − T_jitter) − (T_cq + T_comb + T_su)

Setup slack must be ≥ 0 for the path to pass timing. Negative setup slack means the path is too slow for the given clock period. Increasing the clock period (lower frequency) or shortening the data path are the only remedies.

Section 03

Hold Time (T_h) — Post-Clock Stability

Hold time is the minimum duration data must remain stable after the active clock edge. After the clock triggers, the slave latch takes a finite time (the aperture) to electrically isolate the master. If data changes during this isolation phase, the new data may leak into the captured state.

What causes Hold violations?

Very short combinational paths between registers — the "fast" data arrives at the capture flip-flop before the clock edge has fully isolated the previous value. Common in reset paths, scan chains, and clock domain crossings.

How is Hold violation fixed?

Insert delay buffers on the data path to slow it down. Hold violations cannot be fixed by reducing clock frequency — they are path-delay issues independent of clock period.

Hold check: T_cq + T_comb_min >= T_h + T_skew

Hold Slack = (T_cq + T_comb_min) − (T_h + T_skew)

Critical rule: Hold slack is frequency-independent. Slowing the clock never helps a hold violation. Only adding physical delay on the data path fixes it. This is why hold violations discovered post-silicon require ECO buffers — an expensive fix.

Section 04

Launch & Capture — The Timing Path Model

STA analyzes timing paths, not individual flip-flops. Every path has a launch flip-flop (source) and a capture flip-flop (destination) with combinational logic between them. The clock propagates to both through the clock tree, potentially arriving at different times — this difference is clock skew.

Launch FF                    Capture FF
   │                              │
   │  CLK_L (launch clock)        │  CLK_C (capture clock)
   │                              │
   ├─ Tclk→q ─┬─ Tcomb ──────────► D[setup/hold check]
              │
              └─ (min path for hold)

Data must arrive BEFORE: CLK_C + Tperiod - Tsu   (setup)
Data must arrive AFTER:  CLK_C + Th              (hold)

Clock Skew = CLK_C arrival - CLK_L arrival
  Positive skew: capture clock arrives later → helps setup, hurts hold
  Negative skew: capture clock arrives earlier → hurts setup, helps hold

Complete Setup equation: Slack = T_period + T_skew_positive − T_jitter − T_uncertainty − T_cq − T_comb_max − T_su. All terms on the right subtract from the available clock period.

Section 05

Clock Skew and Clock Jitter

Clock Skew is the spatial difference in clock arrival time between two flip-flops in the same domain, caused by unequal buffer delays in the clock tree. CTS (Clock Tree Synthesis) minimizes skew but cannot eliminate it entirely.

Skew direction	Setup effect	Hold effect
Positive (capture later)	Helps	Hurts
Negative (capture earlier)	Hurts	Helps

Clock Jitter is the cycle-to-cycle variation in the clock period, caused by power supply noise, PLL reference spread, and thermal effects. Unlike skew (which is fixed per pair), jitter is stochastic — it varies each cycle.

Jitter always hurts setup and is modeled conservatively: the full jitter budget is subtracted from the available period. Hold analysis uses a separate jitter model for the minimum path scenario.

Section 06

PVT Corners & Environmental Variation

A chip must meet timing across all manufacturing and operating conditions. STA uses PVT corners — combinations of Process, Voltage, and Temperature — to bracket the worst-case scenarios.

Corner	Process	Voltage	Temperature	Checks	Use case
SS (Slow-Slow)	Slow NMOS + Slow PMOS	Low (0.9V)	High (125°C)	Setup	Automotive, worst-case freq
FF (Fast-Fast)	Fast NMOS + Fast PMOS	High (1.1V)	Low (−40°C)	Hold	Best-case speed, hold risk
TT (Typical)	Nominal	Nominal (1.0V)	Room (25°C)	Power	Power & leakage analysis
SF / FS (Mixed)	Slow N / Fast P	Varied	Varied	Special	Clock/data skew corners

Modern tapeouts check 100+ corners including RC extraction modes (Cmin, Cmax, Cbest), aging (BTI, HCI), and multi-mode scenarios (functional, scan, at-speed test). A chip passing only TT corner is not production-ready.

Section 07

OCV and CPPR — Advanced Pessimism Modeling

On-Chip Variation (OCV) acknowledges that transistors on the same die behave differently due to local doping density, oxide thickness, and lithography variations. Even two identical buffers placed 1mm apart on the same chip will have slightly different delays.

OCV Derating

STA tools apply a derating factor (e.g., 5–15%) to cell delays — slowing the data path and speeding the clock path for setup (or the reverse for hold) to find the true worst case without needing Monte Carlo simulation.

AOCV / POCV

Advanced OCV (AOCV) uses distance and depth-based derating — cells deeper in the clock tree get smaller derate because variation averages out over multiple stages. Parametric OCV (POCV) uses statistical sigma-based models for sign-off.

CPPR (Common Path Pessimism Removal) corrects an over-pessimism introduced by OCV: the portion of the clock tree shared between the launch and capture paths is physically the same silicon, so it cannot be simultaneously fast and slow. CPPR adds back the incorrectly removed margin on this common segment.

Setup slack with OCV: Slack = T_period − (T_data_path × derate_late) − T_su

− (T_clk_capture / derate_early) + T_clk_launch × derate_late

After CPPR: Slack_CPPR = Slack_OCV + T_common_path × (derate_late − derate_early)

Section 08

Metastability — When Timing Fails

When setup or hold time is violated, the flip-flop's internal feedback node may settle to an intermediate voltage between V_IL and V_IH — neither a valid 0 nor 1. This is metastability. Physically, it is the flip-flop's cross-coupled inverters balanced at an unstable equilibrium, like a ball on a hilltop.

Metastability resolves exponentially over time — the output eventually settles to 0 or 1, but the resolution time T_r is unbounded in theory. The MTBF (Mean Time Between Failures) quantifies how long a design is expected to operate before a metastable event propagates to functional logic and causes a failure.

MTBF = exp(T_res / τ) / (f_clk × f_data × T_window)

T_res = available resolution time | τ = flip-flop time constant (process-dependent) | T_window = aperture time

In synchronous design

Metastability in a single clock domain is caused by asynchronous inputs (buttons, off-chip signals, CDC). The fix is a 2-FF synchronizer that gives one full clock period for resolution before the second FF samples.

When metastability escapes

If metastability propagates through combinational logic before resolving, it can cause incorrect branch decisions, memory corruption, or system hang. MTBF must be > 1000 years for high-reliability designs.

Section 09

Engineering Fixes for Timing Violations

Setup Violations (data too slow)

Technique	How it helps
Pipelining	Adds FF mid-path to shorten T_comb
Gate sizing	Larger drive-strength reduces T_comb
Logic restructuring	Reduces gate depth (critical path)
VT swapping	Replace High-V_t cells with Low-V_t
Clock frequency	Increase T_period (lower frequency)

Hold Violations (data too fast)

Technique	How it helps
Buffer insertion	Adds delay on the fast path
High-V_t cells	Slower cells increase T_comb_min
Lockup latch	Absorbs extra hold margin in scan chains
CTS optimization	Adjust skew so capture clock arrives sooner
Never: reduce freq	Hold is frequency-independent — won't help

Section 10

Frequently Asked Questions

Setup time (T_su) is the minimum duration data must be stable before the clock edge — it limits how slow the combinational path can be. Hold time (T_h) is the minimum duration data must stay stable after the clock edge — it limits how fast the combinational path can be. Setup is a frequency-dependent constraint; hold is not.

Hold slack = T_cq + T_comb_min − T_h − T_skew. The clock period (T_period) does not appear in this equation. Both the launch and capture flip-flops see the same clock cycle, so slowing the clock equally delays both the data launch and the capture edge — the race condition between them remains unchanged.

Clock skew is the difference in clock arrival time between the launch and capture flip-flops caused by unequal buffer delays in the clock tree. Positive skew (capture clock arrives later) gives extra time for data to arrive — it helps setup but tightens hold. Negative skew does the reverse. CTS targets < 50ps of local skew in modern designs, but any skew must be accounted for in both setup and hold checks.

On-Chip Variation (OCV) acknowledges that identically designed cells at different locations on the same die have different delays due to local process variation. STA tools apply derating factors — pessimistically making the data path slower and the clock path faster (for setup) — to ensure sign-off without needing full Monte Carlo simulation. Without OCV modeling, chips that pass STA may fail in production silicon.

Common Path Pessimism Removal (CPPR) removes an impossibility that OCV introduces: the shared portion of the launch and capture clock paths (e.g., the root buffer and first few levels of the clock tree) is the same physical silicon. OCV applies contradictory derating (slow for launch, fast for capture) on this shared segment, which is physically impossible. CPPR adds back the over-pessimism for the common segment, producing a realistic but still conservative slack number.

Aperture time = T_su + T_h. It is the total forbidden window around the clock edge during which data must not change. A typical high-speed flip-flop in 7nm CMOS has an aperture of 40–80 ps. If data changes anywhere within this window, the flip-flop output is unreliable. Tighter process nodes have smaller apertures, enabling higher clock frequencies.

Explore Further

D Flip-Flop Design

Understand the internal structure of the flip-flop that setup and hold time physically constrain — master/slave latches, clock-to-Q paths, and metastability inside the cell.

Metastability in RTL

Deep dive into what happens when setup or hold time is violated — how the flip-flop enters an undefined state, MTBF calculation, and 2-FF synchronizer design to contain it.

Reset Synchronizer

See how the same 2-FF synchronizer principle that handles metastability is applied to safely de-assert asynchronous resets in synchronous clock domains.