Full Adder (1-Bit)

By chaining two Half Adders together and adding an OR gate, we create a Full Adder that can accept a Carry-In bit. This allows us to cascade adders sequentially for multi-bit arithmetic.

🔬 INTERACTIVE SILICON SIMULATOR

Input A

Input B

Carry-In (Cin)

SUM (A ⊕ B ⊕ Cin)

CARRY OUT

📊 TRUTH TABLE

A	B	Cin	SUM	Cout

📄 VERILOG RTL

// 1-Bit Full Adder Module
module full_adder (
    input  wire a,
    input  wire b,
    input  wire cin,
    output wire sum,
    output wire cout
);
    wire x1, c1, c2;

    // Half Adder 1
    assign x1 = a ^ b;
    assign c1 = a & b;

    // Half Adder 2
    assign sum = x1 ^ cin;
    assign c2  = x1 & cin;

    // Carry Out
    assign cout = c1 | c2;

endmodule