Stage 1: Combinational Arithmetic
1. Half Adder (1-Bit)
The foundational logic unit of computation. Visualize how XOR and AND gates combine to sum two isolated bits.
2. Full Adder (1-Bit)
Incorporate a Carry-In bit using two cascaded Half Adders to allow chaining for multi-bit arithmetic.
3. 4-Bit Adder / Subtractor
Ripple carry propagation delay, two's complement subtraction, and architectural condition flags (Z, V, N, C).
Stage 2: Execution Datapath (Coming Soon)
4. Complete 32-Bit ALU
Integrating Adders, Logic (AND/OR), and Shifters into a centralized Execution Unit.