Claude for Design Verification Engineers: AI-Assisted SystemVerilog & UVM

# Feature 1: Asynchronous FIFO Depth & Full/Empty Flag Assertions
- Spec Ref: Section 3.2.1 (Dual-Clock FIFO Interface)
- Stimulus Scenarios:
  * TC_01: Single-write followed by single-read (sanity).
  * TC_02: Continuous write stream until `full` asserts; verify write drop on overflow attempt.
  * TC_03: Continuous read stream until `empty` asserts; verify invalid read data on underflow attempt.
  * TC_04: Simultaneous write and read at maximum clock frequency ratio (4:1 and 1:4).
  * TC_05: Randomized backpressure toggling `winc` and `rinc` concurrently.
- Checkers & Assertions:
  * SVA_FIFO_01: No write when `full` is asserted (`winc && full |-> !w_accepted`).
  * SVA_FIFO_02: No read when `empty` is asserted (`rinc && empty |-> !r_valid`).
- Functional Coverage Goals:
  * CP_FIFO_DEPTH: Bins for depth 0, 1, 2..N-1, N (Full).
  * CP_CROSS_CLKS: Cross product of write clock frequencies (100MHz-500MHz) x read clock (50MHz-200MHz).

interface apb_if(input logic PCLK, input logic PRESETn);
  logic [31:0] PADDR;
  logic        PSEL;
  logic        PENABLE;
  logic        PWRITE;
  logic [31:0] PWDATA;
  logic [31:0] PRDATA;
  logic        PREADY;
  logic        PSLVERR;

  // Master Clocking Block: Sample in Preponed (#1step), Drive in Re-NBA (#1ns)
  clocking mck @(posedge PCLK);
    default input #1step output #1ns;
    output PADDR, PSEL, PENABLE, PWRITE, PWDATA;
    input  PRDATA, PREADY, PSLVERR;
  endclocking

  // Passive Monitor Clocking Block: Sample all signals without driving
  clocking mon_ck @(posedge PCLK);
    default input #1step;
    input PADDR, PSEL, PENABLE, PWRITE, PWDATA, PRDATA, PREADY, PSLVERR;
  endclocking

  modport MASTER (clocking mck, input PCLK, PRESETn);
  modport MONITOR (clocking mon_ck, input PCLK, PRESETn);
endinterface

class apb_driver extends uvm_driver #(apb_seq_item);
  `uvm_component_utils(apb_driver)

  virtual apb_if.MASTER vif;

  function new(string name = "apb_driver", uvm_component parent = null);
    super.new(name, parent);
  endfunction

  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    if (!uvm_config_db#(virtual apb_if.MASTER)::get(this, "", "vif", vif)) begin
      `uvm_fatal("NO_VIF", {"Virtual interface must be set for: ", get_full_name(), ".vif"})
    end
  endfunction

  task run_phase(uvm_phase phase);
    // Reset bus signals to idle
    vif.mck.PSEL    <= 1'b0;
    vif.mck.PENABLE <= 1'b0;
    vif.mck.PWRITE  <= 1'b0;
    vif.mck.PADDR   <= '0;
    vif.mck.PWDATA  <= '0;

    wait(vif.PRESETn === 1'b1);
    @(vif.mck);

    forever begin
      seq_item_port.get_next_item(req);
      drive_transfer(req);
      seq_item_port.item_done();
    end
  endtask

  task drive_transfer(apb_seq_item item);
    // APB Setup Phase: Assert PSEL, drive Address and Write Control
    @(vif.mck);
    vif.mck.PADDR   <= item.addr;
    vif.mck.PWRITE  <= item.write;
    vif.mck.PSEL    <= 1'b1;
    vif.mck.PENABLE <= 1'b0;
    if (item.write) vif.mck.PWDATA <= item.data;

    // APB Access Phase: Assert PENABLE
    @(vif.mck);
    vif.mck.PENABLE <= 1'b1;

    // Wait for Slave PREADY
    while (!vif.mck.PREADY) @(vif.mck);

    // Capture Read Data if Read Transfer
    if (!item.write) item.data = vif.mck.PRDATA;
    item.slverr = vif.mck.PSLVERR;

    // Return to Idle
    @(vif.mck);
    vif.mck.PSEL    <= 1'b0;
    vif.mck.PENABLE <= 1'b0;
  endtask
endclass

class axi_packet extends uvm_sequence_item;
  typedef enum bit [1:0] {FIXED = 2'b00, INCR = 2'b01, WRAP = 2'b10} burst_e;
  typedef enum bit [2:0] {BYTE = 3'b000, HALF = 3'b001, WORD = 3'b010, QUAD = 3'b011} size_e;

  rand bit [31:0]  addr;
  rand bit [7:0]   len;
  rand size_e      size;
  rand burst_e     burst;
  rand bit [31:0]  data_payload[];

  // 1. Solve burst type before address to ensure wrap alignment
  constraint c_order { solve burst before addr; }

  // 2. Wrap burst length must be 2, 4, 8, or 16
  constraint c_wrap_len {
    if (burst == WRAP) {
      len inside {1, 3, 7, 15}; // AxLEN = burst_length - 1
    }
  }

  // 3. Address alignment for wrapping bursts
  constraint c_wrap_align {
    if (burst == WRAP) {
      (addr % (1 << size)) == 0;
    }
  }

  // 4. Payload size must match burst length
  constraint c_payload_size {
    data_payload.size() == (len + 1);
  }

  // 5. Soft default: prefer word-aligned transfers
  constraint c_default_size {
    soft size == WORD;
  }

  `uvm_object_utils_begin(axi_packet)
    `uvm_field_int(addr, UVM_ALL_ON)
    `uvm_field_int(len, UVM_ALL_ON)
    `uvm_field_enum(size_e, size, UVM_ALL_ON)
    `uvm_field_enum(burst_e, burst, UVM_ALL_ON)
    `uvm_field_array_int(data_payload, UVM_ALL_ON)
  `uvm_object_utils_end

  function new(string name = "axi_packet"); super.new(name); endfunction
endclass

module handshake_sva #(parameter WIDTH = 32) (
  input logic             clk,
  input logic             rst_n,
  input logic             valid,
  input logic             ready,
  input logic [WIDTH-1:0] data
);

  // Property 1: Stability Rule - Once VALID is asserted, VALID and DATA must remain
  // stable until READY is asserted by the receiver.
  property p_valid_stability;
    @(posedge clk) disable iff (!rst_n)
    (valid && !ready) |=> (valid && $stable(data));
  endproperty
  a_valid_stability: assert property(p_valid_stability)
    else $error("[SVA_ERR] VALID dropped or DATA mutated while waiting for READY!");

  // Property 2: No X/Z on Handshake Signals during Active Operation
  property p_no_unknown_handshake;
    @(posedge clk) disable iff (!rst_n)
    !$isunknown(valid) && (valid |-> !$isunknown(data));
  endproperty
  a_no_unknown_handshake: assert property(p_no_unknown_handshake)
    else $error("[SVA_ERR] X or Z state detected on VALID or DATA payload!");

  // Cover Property: Observe full handshake transfer
  c_handshake_transfer: cover property(
    @(posedge clk) disable iff (!rst_n)
    valid && ready
  );
endmodule

class axi4_coverage_subscriber extends uvm_subscriber #(axi4_transaction);
  `uvm_component_utils(axi4_coverage_subscriber)

  axi4_transaction tr_queue[$];
  axi4_transaction cur_tr;

  // Covergroup definition with sampling argument
  covergroup axi4_cg with function sample(axi4_transaction tr);
    option.per_instance = 1;
    option.comment      = "AXI4 Protocol & Boundary Coverage Model";
    option.goal         = 100;

    // Coverpoint 1: Burst Lengths (AxLEN: 0=1 beat, 255=256 beats)
    cp_burst_len: coverpoint tr.len {
      bins single_beat       = {0};
      bins short_burst       = {[1:7]};
      bins medium_burst      = {[8:63]};
      bins max_burst_axi3    = {15};      // AXI3 legacy limit
      bins max_burst_axi4    = {255};     // AXI4 full limit
      bins unaligned_lengths = {[64:254]};
    }

    // Coverpoint 2: Burst Type (FIXED, INCR, WRAP)
    cp_burst_type: coverpoint tr.burst {
      bins fixed = {2'b00};
      bins incr  = {2'b01};
      bins wrap  = {2'b10};
      illegal_bins reserved = {2'b11};
    }

    // Coverpoint 3: 4KB Boundary Crossing Address Analysis
    // AXI spec strictly forbids bursts crossing 4KB page boundaries!
    cp_addr_alignment: coverpoint (tr.addr[11:0]) {
      bins page_start       = {12'h000};
      bins near_4k_page_end = {[12'hFE0:12'hFFF]};
      bins mid_page         = default;
    }

    // Coverpoint 4: Response Status (OKAY, EXOKAY, SLVERR, DECERR)
    cp_resp: coverpoint tr.resp {
      bins okay   = {2'b00};
      bins exokay = {2'b01};
      bins slverr = {2'b10};
      bins decerr = {2'b11};
    }

    // Coverpoint 5: Transition Bins (Back-to-back response transitions)
    cp_resp_transition: coverpoint tr.resp {
      bins okay_to_slverr = (2'b00 => 2'b10);
      bins slverr_to_okay = (2'b10 => 2'b00);
      bins decerr_recovery = (2'b11 => 2'b00);
    }

    // Cross Coverage: Burst Type X Burst Length
    cross_burst_type_len: cross cp_burst_type, cp_burst_len {
      // WRAP bursts must have length 2, 4, 8, or 16 according to ARM AXI Spec!
      ignore_bins illegal_wrap_len = binsof(cp_burst_type.wrap) &&
                                     !binsof(cp_burst_len) intersect {1, 3, 7, 15};
    }

    // Cross Coverage: Address Boundary X Burst Length
    cross_page_crossing: cross cp_addr_alignment, cp_burst_len;
  endgroup

  function new(string name, uvm_component parent);
    super.new(name, parent);
    axi4_cg = new();
  endfunction

  virtual function void write(axi4_transaction t);
    cur_tr = t;
    axi4_cg.sample(cur_tr);
  endfunction
endclass

UVM_FATAL @ 10000000000 ps: reporter [PH_TIMEOUT] Default timeout of 10000000000 ps hit
--- UVM Report catcher summary ---
Total objections outstanding: 1
+-----------------------------------------------------------------------------------------+
| Object                                       | Count | Description                     |
+-----------------------------------------------------------------------------------------+
| uvm_test_top.env.axi_agent.sequencer.vseq    | 1     | axi4_random_traffic_vseq        |
+-----------------------------------------------------------------------------------------+

module axi4_channel_sva #(parameter WIDTH = 64) (
  input logic             clk,
  input logic             rst_n,
  input logic             valid,
  input logic             ready,
  input logic [WIDTH-1:0] data
);

  // Property: Stability until acknowledged
  property p_handshake_stability;
    @(posedge clk) disable iff (!rst_n)
    (valid && !ready) |=> (valid && $stable(data));
  endproperty
  assert_handshake_stability: assert property(p_handshake_stability)
    else $error("[AXI_ERR_01] Master modified data or de-asserted VALID before READY was high!");

  // Property: No combinational loop (READY must not depend combinatorially on VALID in Master)
  // Verified formally in JasperGold or with strict timing assertions
  property p_valid_no_x;
    @(posedge clk) disable iff (!rst_n)
    !$isunknown(valid);
  endproperty
  assert_valid_no_x: assert property(p_valid_no_x)
    else $error("[AXI_ERR_02] VALID signal contains X or Z!");

  // Coverage: Measure handshake latency distribution
  cover_zero_wait: cover property(
    @(posedge clk) disable iff (!rst_n)
    valid && ready
  );

  cover_slave_backpressure: cover property(
    @(posedge clk) disable iff (!rst_n)
    valid && !ready [*3] ##1 (valid && ready)
  );
endmodule

#!/usr/bin/env python3
"""
regression_cluster.py - ASIC Regression Log Analyzer & Failure Classifier
Usage: python regression_cluster.py --log-dir ./sim_results --out report.md
"""

import os
import re
import sys
import argparse
from collections import defaultdict

ERROR_PATTERNS = [
    re.compile(r"(UVM_FATAL\s+.*)", re.MULTILINE),
    re.compile(r"(UVM_ERROR\s+.*?:\s+\[(.*?)\]\s+(.*))", re.MULTILINE),
    re.compile(r"(\*E,ASSERT\s+.*)", re.MULTILINE),
    re.compile(r"(Assertion\s+`.*?'\s+failed.*)", re.MULTILINE),
    re.compile(r"(Segmentation fault.*)", re.MULTILINE),
    re.compile(r"(PH_TIMEOUT\s+.*)", re.MULTILINE)
]

SEED_PATTERN = re.compile(r"(?:-seed|\+ntb_random_seed=|\+seed=)\s*(\d+)", re.IGNORECASE)

def parse_log(filepath):
    """Scans a single simulation log file for errors and seed."""
    with open(filepath, 'r', errors='ignore') as f:
        content = f.read()

    seed = "Unknown"
    seed_match = SEED_PATTERN.search(content)
    if seed_match:
        seed = seed_match.group(1)

    # Check for passed status
    if "TEST PASSED" in content or "UVM_TEST_TOP: PASSED" in content:
        return "PASS", seed, None

    # Search for error signatures
    for pattern in ERROR_PATTERNS:
        match = pattern.search(content)
        if match:
            # Normalize error signature to remove variable time/memory addresses
            sig = match.group(0).strip()
            sig = re.sub(r"@\s*\d+\s*(?:ps|ns|fs)", "@ ", sig)
            sig = re.sub(r"0x[0-9a-fA-F]+", "0x", sig)
            return "FAIL", seed, sig

    if "UVM_ERROR" in content or "Fatal error" in content:
        return "FAIL", seed, "Unclassified Simulation Error"

    return "UNKNOWN", seed, None

def run_analysis(log_dir):
    clusters = defaultdict(list)
    pass_count = 0
    fail_count = 0
    unknown_count = 0

    for root, _, files in os.walk(log_dir):
        for file in files:
            if file.endswith((".log", ".rpt", ".txt")):
                path = os.path.join(root, file)
                status, seed, sig = parse_log(path)
                if status == "PASS":
                    pass_count += 1
                elif status == "FAIL":
                    fail_count += 1
                    clusters[sig].append((file, seed))
                else:
                    unknown_count += 1

    total = pass_count + fail_count + unknown_count
    pass_rate = (pass_count / total * 100) if total > 0 else 0.0

    print(f"[SUMMARY] Total: {total} | Pass: {pass_count} ({pass_rate:.1f}%) | Fail: {fail_count} | Unique Clusters: {len(clusters)}")
    return total, pass_count, fail_count, clusters

if __name__ == "__main__":
    parser = argparse.ArgumentParser(description="ASIC Regression Analyzer")
    parser.add_argument("--log-dir", required=True, help="Directory containing log files")
    args = parser.parse_args()
    run_analysis(args.log_dir)

// Project 1: Complete Self-Checking APB Testbench
`timescale 1ns/1ps

// 1. APB Interface with Clocking Block
interface apb_if(input logic pclk);
  logic        preset_n;
  logic [31:0] paddr;
  logic        psel;
  logic        penable;
  logic        pwrite;
  logic [31:0] pwdata;
  logic [3:0]  pstrb;
  logic [31:0] prdata;
  logic        pready;
  logic        pslverr;

  // Master Clocking Block to eliminate race conditions
  clocking mck @(posedge pclk);
    default input #1step output #1ns;
    output paddr, psel, penable, pwrite, pwdata, pstrb;
    input  prdata, pready, pslverr;
  endclocking
endinterface

// 2. Transaction Class with Constraints
class apb_trans;
  rand bit [31:0] addr;
  rand bit [31:0] data;
  rand bit        write;
  rand bit [3:0]  strb;
  bit [31:0]      rdata;
  bit             slverr;

  constraint c_addr_aligned { addr[1:0] == 2'b00; }
  constraint c_addr_range   { addr < 32'h0000_1000; }
  constraint c_strb_valid   { strb inside {4'b1111, 4'b0011, 4'b1100, 4'b0001}; }
endclass

// 3. Scoreboard Class using Associative Memory Model
class apb_scoreboard;
  bit [31:0] mem[int];
  int match_count = 0;
  int error_count = 0;

  function void check_write(bit [31:0] addr, bit [31:0] data);
    mem[addr] = data;
    $display("[SB_WRITE] Stored Addr: 0x%08h | Data: 0x%08h", addr, data);
  endfunction

  function void check_read(bit [31:0] addr, bit [31:0] actual_data);
    if (!mem.exists(addr)) begin
      $display("[SB_WARN] Read from unwritten addr 0x%08h!", addr);
    end else if (mem[addr] === actual_data) begin
      match_count++;
      $display("[SB_PASS] Match @ 0x%08h: Exp=0x%08h, Act=0x%08h", addr, mem[addr], actual_data);
    end else begin
      error_count++;
      $error("[SB_FAIL] Mismatch @ 0x%08h: Exp=0x%08h, Act=0x%08h", addr, mem[addr], actual_data);
    end
  endfunction

  function void report();
    $display("========================================");
    $display("SCOREBOARD REPORT: Matches=%0d, Errors=%0d", match_count, error_count);
    $display("========================================");
  endfunction
endclass

// 4. Testbench Environment
program automatic apb_test(apb_if vif);
  apb_scoreboard sb = new();

  task automatic drive_write(apb_trans tr);
    @(vif.mck);
    vif.mck.psel    <= 1'b1;
    vif.mck.pwrite  <= 1'b1;
    vif.mck.paddr   <= tr.addr;
    vif.mck.pwdata  <= tr.data;
    vif.mck.pstrb   <= tr.strb;
    vif.mck.penable <= 1'b0;

    @(vif.mck);
    vif.mck.penable <= 1'b1;
    while (!vif.mck.pready) @(vif.mck);

    sb.check_write(tr.addr, tr.data);
    @(vif.mck);
    vif.mck.psel    <= 1'b0;
    vif.mck.penable <= 1'b0;
  endtask

  task automatic drive_read(apb_trans tr);
    @(vif.mck);
    vif.mck.psel    <= 1'b1;
    vif.mck.pwrite  <= 1'b0;
    vif.mck.paddr   <= tr.addr;
    vif.mck.penable <= 1'b0;

    @(vif.mck);
    vif.mck.penable <= 1'b1;
    while (!vif.mck.pready) @(vif.mck);

    tr.rdata = vif.mck.prdata;
    sb.check_read(tr.addr, tr.rdata);
    @(vif.mck);
    vif.mck.psel    <= 1'b0;
    vif.mck.penable <= 1'b0;
  endtask

  initial begin
    apb_trans tr = new();
    vif.preset_n <= 1'b0;
    repeat (5) @(vif.mck);
    vif.preset_n <= 1'b1;

    // Run 50 randomized write-read verification cycles
    for (int i = 0; i < 50; i++) begin
      assert(tr.randomize());
      drive_write(tr);
      drive_read(tr);
    end

    sb.report();
    $finish;
  end
endprogram

`include "uvm_macros.svh"
import uvm_pkg::*;

// Agent Configuration Object
class protocol_agent_config extends uvm_object;
  `uvm_object_utils(protocol_agent_config)
  uvm_active_passive_enum is_active = UVM_ACTIVE;
  virtual protocol_if     vif;

  function new(string name = "protocol_agent_config");
    super.new(name);
  endfunction
endclass

// Driver Component
class protocol_driver extends uvm_driver #(protocol_seq_item);
  `uvm_component_utils(protocol_driver)
  virtual protocol_if vif;

  function new(string name, uvm_component parent);
    super.new(name, parent);
  endfunction

  virtual task run_phase(uvm_phase phase);
    protocol_seq_item req;
    forever begin
      seq_item_port.get_next_item(req);
      drive_transfer(req);
      seq_item_port.item_done();
    end
  endtask

  virtual task drive_transfer(protocol_seq_item req);
    @(vif.drv_cb);
    vif.drv_cb.valid <= 1'b1;
    vif.drv_cb.data  <= req.data;
    do begin
      @(vif.drv_cb);
    end while (!vif.drv_cb.ready);
    vif.drv_cb.valid <= 1'b0;
  endtask
endclass

// Monitor Component with TLM Analysis Port
class protocol_monitor extends uvm_monitor;
  `uvm_component_utils(protocol_monitor)
  virtual protocol_if vif;
  uvm_analysis_port #(protocol_seq_item) item_collected_port;

  function new(string name, uvm_component parent);
    super.new(name, parent);
    item_collected_port = new("item_collected_port", this);
  endfunction

  virtual task run_phase(uvm_phase phase);
    protocol_seq_item tr;
    forever begin
      @(vif.mon_cb);
      if (vif.mon_cb.valid && vif.mon_cb.ready) begin
        tr = protocol_seq_item::type_id::create("tr");
        tr.data = vif.mon_cb.data;
        item_collected_port.write(tr);
      end
    end
  endtask
endclass

// Sequencer Typedef
typedef uvm_sequencer #(protocol_seq_item) protocol_sequencer;

// Reusable Agent Encapsulation
class protocol_agent extends uvm_agent;
  `uvm_component_utils(protocol_agent)

  protocol_driver       driver;
  protocol_monitor      monitor;
  protocol_sequencer    sequencer;
  protocol_agent_config cfg;
  uvm_analysis_port #(protocol_seq_item) item_collected_port;

  function new(string name, uvm_component parent);
    super.new(name, parent);
  endfunction

  virtual function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    if (!uvm_config_db#(protocol_agent_config)::get(this, "", "cfg", cfg))
      `uvm_fatal("NOCFG", "Agent config not found in uvm_config_db!")

    monitor = protocol_monitor::type_id::create("monitor", this);
    monitor.vif = cfg.vif;

    if (cfg.is_active == UVM_ACTIVE) begin
      driver    = protocol_driver::type_id::create("driver", this);
      sequencer = protocol_sequencer::type_id::create("sequencer", this);
      driver.vif = cfg.vif;
    end
  endfunction

  virtual function void connect_phase(uvm_phase phase);
    super.connect_phase(phase);
    item_collected_port = monitor.item_collected_port;
    if (cfg.is_active == UVM_ACTIVE) begin
      driver.seq_item_port.connect(sequencer.seq_item_export);
    end
  endfunction
endclass

`uvm_analysis_imp_decl(_push)
`uvm_analysis_imp_decl(_pop)

class fifo_scoreboard #(type T = fifo_item) extends uvm_scoreboard;
  `uvm_component_param_utils(fifo_scoreboard #(T))

  uvm_analysis_imp_push #(T, fifo_scoreboard #(T)) push_export;
  uvm_analysis_imp_pop  #(T, fifo_scoreboard #(T)) pop_export;

  T expected_queue[$];
  int match_count = 0;
  int mismatch_count = 0;

  function new(string name, uvm_component parent);
    super.new(name, parent);
    push_export = new("push_export", this);
    pop_export  = new("pop_export", this);
  endfunction

  virtual function void write_push(T item);
    T cloned_item;
    $cast(cloned_item, item.clone());
    expected_queue.push_back(cloned_item);
    `uvm_info("SB_PUSH", $sformatf("Enqueued item. Queue depth: %0d", expected_queue.size()), UVM_HIGH)
  endfunction

  virtual function void write_pop(T act_item);
    if (expected_queue.size() == 0) begin
      mismatch_count++;
      `uvm_error("SB_UNDERFLOW", "Pop received from DUT when expected queue was empty!")
      return;
    end

    T exp_item = expected_queue.pop_front();
    if (exp_item.compare(act_item)) begin
      match_count++;
      `uvm_info("SB_MATCH", "FIFO data packet matched golden model successfully", UVM_HIGH)
    end else begin
      mismatch_count++;
      `uvm_error("SB_MISMATCH", $sformatf("Data mismatch!
Expected: %s
Actual:   %s",
                 exp_item.sprint(), act_item.sprint()))
    end
  endfunction

  virtual function void check_phase(uvm_phase phase);
    super.check_phase(phase);
    if (expected_queue.size() != 0) begin
      `uvm_error("SB_LEAK", $sformatf("Simulation ended with %0d unconsumed items left in FIFO queue!",
                 expected_queue.size()))
    end else begin
      `uvm_info("SB_CLEAN", $sformatf("Scoreboard clean sign-off: %0d matched transfers verified.", match_count), UVM_LOW)
    end
  endfunction
endclass

module ready_valid_sva #(
  parameter WIDTH = 64,
  parameter MAX_WAIT = 16
)(
  input logic             clk,
  input logic             rst_n,
  input logic             valid,
  input logic             ready,
  input logic [WIDTH-1:0] data
);

  // Property 1: Stability Rule - Data and Valid cannot change while stalled
  property p_stability;
    @(posedge clk) disable iff (!rst_n)
    (valid && !ready) |=> (valid && $stable(data));
  endproperty
  assert_stability: assert property(p_stability)
    else $error("[SVA_STABILITY_FAIL] VALID dropped or DATA changed while waiting for READY!");

  // Property 2: Liveness Rule - Receiver must assert READY within MAX_WAIT cycles
  property p_liveness;
    @(posedge clk) disable iff (!rst_n)
    valid |=> ##[0:MAX_WAIT] ready;
  endproperty
  assert_liveness: assert property(p_liveness)
    else $error("[SVA_LIVENESS_FAIL] READY was not asserted within %0d cycles of VALID!", MAX_WAIT);

  // Property 3: No Unknowns (X/Z) on payload during transfer
  property p_no_x_on_valid;
    @(posedge clk) disable iff (!rst_n)
    valid |-> !$isunknown(data);
  endproperty
  assert_no_x: assert property(p_no_x_on_valid)
    else $error("[SVA_X_DETECTED] Payload contains unknown state (X/Z) while VALID is asserted!");

  // Property 4: Reset Deassertion - VALID must be 0 immediately upon reset
  property p_reset_state;
    @(posedge clk)
    !rst_n |-> (valid == 1'b0);
  endproperty
  assert_reset: assert property(p_reset_state)
    else $error("[SVA_RST_FAIL] VALID asserted during active reset!");

  // Cover Properties: Confirm testbench exercises boundary scenarios
  cover_zero_latency_transfer: cover property(
    @(posedge clk) disable iff (!rst_n)
    valid && ready
  );

  cover_backpressure_burst: cover property(
    @(posedge clk) disable iff (!rst_n)
    valid && !ready [*4] ##1 (valid && ready)
  );
endmodule

#!/usr/bin/env python3
"""
dv_log_triage.py - ASIC Regression Log Analyzer & Failure Clustering Engine
"""
import os
import re
import sys
import json
from collections import defaultdict

REGEX_PATTERNS = {
    "UVM_ERROR": re.compile(r"UVM_ERROR\s+(?:(?:\S+)\((\d+)\))?\s*:\s*(?:reporter|[\w\.]+)\s*\[(.*?)\]\s*(.*)"),
    "UVM_FATAL": re.compile(r"UVM_FATAL\s+(?:(?:\S+)\((\d+)\))?\s*:\s*(?:reporter|[\w\.]+)\s*\[(.*?)\]\s*(.*)"),
    "SVA_ASSERT": re.compile(r"\*E,ASSERT\s+\((\w+)\):\s+(.*)"),
    "SIM_CRASH": re.compile(r"(Segmentation fault|Internal compiler error|core dumped)"),
}
SEED_RE = re.compile(r"(?:-seed|\+ntb_random_seed=|\+seed=)\s*(\d+)")

def triage_log(filepath):
    with open(filepath, 'r', errors='ignore') as f:
        content = f.read()

    seed = "0"
    sm = SEED_RE.search(content)
    if sm:
        seed = sm.group(1)

    if "UVM_TEST_TOP: PASSED" in content or "TEST PASSED" in content:
        return "PASS", seed, None

    for err_type, pat in REGEX_PATTERNS.items():
        m = pat.search(content)
        if m:
            raw_sig = m.group(0).strip()
            # Normalize timestamps, pointers and random line numbers
            norm_sig = re.sub(r"@\s*\d+\s*(?:ps|ns)", "@ ", raw_sig)
            norm_sig = re.sub(r"0x[0-9a-fA-F]+", "0x", norm_sig)
            return "FAIL", seed, f"[{err_type}] {norm_sig[:120]}"

    return "FAIL", seed, "[UNKNOWN_FAIL] Simulation terminated without pass marker"

def main():
    if len(sys.argv) < 2:
        print("Usage: python dv_log_triage.py ")
        sys.exit(1)

    log_dir = sys.argv[1]
    clusters = defaultdict(list)
    passed, failed = 0, 0

    for root, _, files in os.walk(log_dir):
        for f in files:
            if f.endswith((".log", ".rpt", ".out")):
                path = os.path.join(root, f)
                status, seed, sig = triage_log(path)
                if status == "PASS":
                    passed += 1
                else:
                    failed += 1
                    clusters[sig].append({"file": f, "seed": seed})

    total = passed + failed
    pass_pct = (passed / total * 100) if total > 0 else 0.0

    print(f"# REGRESSION SUMMARY REPORT")
    print(f"- **Total Tests:** {total}")
    print(f"- **Passed:** {passed} ({pass_pct:.2f}%)")
    print(f"- **Failed:** {failed}")
    print(f"- **Unique Failure Clusters:** {len(clusters)}
")
    print("| Count | Error Signature | Example Reproduce Command |")
    print("|---|---|---|")
    for sig, runs in sorted(clusters.items(), key=lambda x: len(x[1]), reverse=True):
        cnt = len(runs)
        sample = runs[0]
        cmd = f"simv +ntb_random_seed={sample['seed']} -l debug.log"
        print(f"| **{cnt}** | `{sig}` | `{cmd}` |")

if __name__ == "__main__":
    main()

#!/usr/bin/env python3
"""
sanitize_dv_code.py - Anonymizes proprietary ASIC IP and SystemVerilog code
"""
import re
import sys

# Replace proprietary codenames with generic engineering identifiers
SUBSTITUTIONS = [
    (r"project_titan", "soc_top"),
    (r"secure_vault_crypto", "security_engine"),
    (r"nvidia_\w+", "custom_ip"),
    (r"qualcomm_\w+", "custom_ip"),
    (r"0x[0-9a-fA-F]{8,}", "0x1000_0000"),  # Anonymize proprietary base addresses
]

def sanitize(code_text):
    # 1. Strip multi-line and single-line internal comments
    code_text = re.sub(r"/\*[\s\S]*?\*/", "", code_text)
    code_text = re.sub(r"//.*", "", code_text)

    # 2. Perform identifier replacements
    for pattern, replacement in SUBSTITUTIONS:
        code_text = re.sub(pattern, replacement, code_text, flags=re.IGNORECASE)

    # 3. Clean trailing whitespace
    lines = [line.rstrip() for line in code_text.splitlines() if line.strip()]
    return "
".join(lines)

if __name__ == "__main__":
    if len(sys.argv) < 2:
        print("Usage: python sanitize_dv_code.py ")
        sys.exit(1)
    with open(sys.argv[1], 'r') as f:
        sanitized = sanitize(f.read())
    print(sanitized)