Floorplanning — Step by Step
The first and most critical step of physical design — where die size, macro positions, and power networks are decided. A bad floorplan cannot be fixed downstream.
1. What is Floorplanning?
Floorplanning is the first physical design step that converts a synthesized gate-level netlist into a spatial plan for the chip. It defines where everything lives on silicon before a single standard cell is placed.
The floorplan decision sets the boundaries for everything that follows — timing, congestion, power, area. A good floorplan makes timing closure straightforward; a bad one can make it impossible regardless of how much effort is applied later.
Synthesis → Floorplanning → Placement → CTS → Routing → Sign-off
Floorplanning is Step 1 of physical implementation. It happens after logic synthesis and before standard cell placement.
What floorplanning decides
- Die size and core area — overall chip dimensions and the region where logic lives
- IO pad placement — where input/output pins sit on the die boundary
- Hard macro placement — fixed positions for SRAMs, ROMs, PLLs, analog IP
- Power distribution network (PDN) — rings, stripes, rails for VDD and VSS
- Placement blockages — regions where standard cells cannot be placed
- Power domain boundaries — for multi-voltage / low-power designs
2. Inputs & Outputs
- Gate-level netlist (post-synthesis)
- Technology LEF — metal layers, design rules
- Cell LEF — standard cell dimensions, pin locations
- Macro LEF/GDS — hard macro sizes and pin locations
- SDC constraints — clocks, I/O timing, exceptions
- UPF/CPF — power domain definitions
- Floorplan specification — target die size, utilization
- Pin assignment file — IO pad order
- DEF (Design Exchange Format) — floorplan layout
- Placed macros with fixed positions
- IO pad positions
- Power ring and stripe definitions
- Placement and routing blockages
- Pre-placement timing report (sanity check)
- Early congestion estimate map
3. Floorplanning Flow — Step by Step
Die Sizing & Core Area Definition
Calculate the minimum die area based on total standard cell area and target utilization. Define the core boundary (where logic lives) and the IO ring area around it. Set the aspect ratio (width ÷ height).
IO Pad / Pin Placement
Place IO pads or signal pins on the die boundary. Group related IOs together (data bus, clock, power). For pad-limited designs, IO spacing constraints drive the die size. For core-limited designs, IO placement is flexible.
Hard Macro Placement
Place SRAMs, ROMs, PLLs, and other hard macros at fixed positions. Follow macro placement guidelines — edges, not islands. Align to power grid. Verify channel widths between macros. Add halos around each macro.
Power Planning (PDN Creation)
Create the power distribution network: core power ring → power stripes across the core → standard cell rails at M1. Run early IR drop analysis. Adjust stripe width and pitch until IR drop is within target (< 5% of VDD).
Placement Blockage Definition
Define regions where standard cells must not be placed — analog keep-out areas, areas reserved for custom routing, regions near IO pads, and above-macro blockages for routing-only layers.
Floorplan Verification & Iteration
Run pre-placement timing (estimate wire loads), congestion estimation, and power grid IR drop. If any metric is out of spec, iterate on macro positions or die size before handing off to placement.
4. Die Sizing & Core Utilization
The first numerical decision in floorplanning. The core area must be large enough to fit all logic but small enough to keep the die economical.
Key formulas
| Parameter | Formula | Typical range |
|---|---|---|
| Core Utilization | Total std-cell area ÷ Core area × 100% | 60 – 80% |
| Core Area | Total std-cell area ÷ Target utilization | — |
| Aspect Ratio | Core width ÷ Core height | 0.5 – 2.0 |
| Die Area | Core area + IO ring + margins | — |
| Routing overhead | ~20–30% of std-cell area for routing wires | — |
Post-synthesis total cell area = 2.5 mm². Target utilization = 70%.
Core area = 2.5 / 0.70 = 3.57 mm² → core = ~1.89 mm × 1.89 mm (square, AR=1.0).
Die = core + IO ring (~200 μm each side) → die ≈ 2.29 mm × 2.29 mm.
Every 5% increase in utilization roughly doubles routing congestion in the hottest regions. At 80%+ utilization, the placer has little freedom to spread cells, and the router runs out of tracks. If timing closure is hard, reducing utilization by 5–10% often saves weeks of effort.
5. Floorplan Diagram
A typical chip floorplan showing die boundary, IO pads, hard macros, standard cell areas, and power grid.
Fig 1 — Typical chip floorplan: IO ring, power ring + stripes, corner macros (SRAM×2, PLL, ROM), center standard cell area
6. IO Pad Placement
IO pads (or signal pins in internal blocks) sit on the die perimeter. Their placement affects:
- Routing congestion near edges — all routes to/from IOs must enter the core through a narrow boundary region
- Clock IO location — the clock pad should be near the PLL and central to minimize clock tree length
- Bus grouping — a 32-bit data bus should have all 32 pins on the same edge to avoid long cross-chip routing
- Power/ground pads — evenly distributed around the perimeter to minimize IR drop in the IO ring
Pad-limited vs Core-limited
| Type | Limiting factor | Die size determined by | Typical for |
|---|---|---|---|
| Pad-limited | Too many IO pads, not enough perimeter | IO count × pad pitch × 4 sides | Low-logic, many IO chips (microcontrollers, mixed-signal) |
| Core-limited | Logic area too large for die | Core utilization and cell area | Complex SoCs, processors, AI accelerators |
7. Hard Macro Placement Guidelines
Macro placement is the most art-and-science step in floorplanning. Poor macro placement is the #1 cause of congestion and timing closure failures in physical design.
Core rules
- Place macros at edges or corners — not in the middle of the core. Macros are routing obstacles; placing them at boundaries leaves a clear routing channel for standard cells in the center.
- Align macro edges to power grid — macros need VDD/VSS connections at their boundaries. Misalignment wastes stripes.
- Minimum channel width ≥ 10× standard cell height — the routing channel between two macros must be wide enough for signal and power routes to pass.
- Group related macros together — data SRAM next to the datapath, instruction SRAM near the fetch unit. Short data connections → fewer routing tracks consumed.
- Orient macro pins toward the logic that connects to them — if a SRAM's address port faces the datapath, connections are short. Facing the wrong way wastes routing tracks.
Macro halo
A macro halo is an exclusion zone placed automatically around every hard macro, typically 2–5 μm wide. Standard cells cannot be placed inside the halo. The halo ensures:
- Routing channels exist at macro boundaries for signal connections
- Power connections can reach macro power pins
- No DRC violations from std-cell to macro metal layer interactions
8. Power Planning
The Power Distribution Network (PDN) is built during floorplanning. Every standard cell and macro needs clean, low-resistance VDD and VSS connections. IR drop (voltage drop due to resistance) must stay below ~5% of VDD.
Fig 2 — Power grid structure: ring → vertical VDD/VSS stripes (Mn) → horizontal M1 rails → standard cell VDD/VSS pins
PDN design parameters
| Parameter | Typical value | Effect of increasing |
|---|---|---|
| Stripe width | 2–10 μm | Lower resistance → less IR drop, but consumes more routing tracks |
| Stripe pitch | 50–200 μm | More stripes → lower IR drop, but more routing blockage overhead |
| Metal layer | M5–M9 for stripes | Upper metals are thicker → lower resistance; reserved for power use |
| Ring width | 10–30 μm | Wider ring = lower ring resistance, better current distribution |
Static IR drop must be <5% of VDD. At VDD=0.75V (advanced node), that means <37.5 mV drop from power pad to the worst cell. Exceeding this causes functional failures (setup violations, logic errors). Dynamic IR drop during simultaneous switching events can be 2–3× static — must also be checked.
9. Placement Blockages
Blockages tell the placer where standard cells cannot go. Defined during floorplanning, they protect critical regions.
| Blockage type | What it blocks | Typical use case |
|---|---|---|
| Hard Placement Blockage | No standard cells at all | Above hard macros, analog keep-out zones, reserved custom routing areas |
| Soft Placement Blockage | Placer avoids but may use if necessary | Regions where lower cell density is preferred (near die edge, near high-power macros) |
| Partial Blockage | Limits utilization to X% in region | Near macro halos, IO landing zones — allow some cells but not full density |
| Routing Blockage | No routing on specified layers | RF keep-out (no digital metal above RF analog), above-pad blockages |
| Macro Halo (auto) | No cells within N μm of macro edge | Automatically added around every hard macro during floorplan |
10. Floorplan Quality Checks
Before handing off to placement, validate the floorplan against these criteria:
| Check | Target | Tool |
|---|---|---|
| Core utilization | 60–80% | Innovus / ICC2 report |
| Routing congestion estimate | <80% routing demand/supply ratio in hottest region | Congestion map (early global route) |
| IR drop (static) | <5% VDD at worst node | Apache RedHawk / Voltus (early analysis) |
| Pre-placement WNS | Negative slack should be <10–20% of clock period | Primetime / Innovus timer |
| Macro legality | All macros on grid, no overlap, no out-of-bounds | DRC checker in PD tool |
| Channel widths | All channels ≥ 10× std-cell height | Manual / script check |
| IO pin accessibility | All pins reachable without routing blockage | Connectivity check |
Floorplanning is highly iterative. A typical design goes through 3–10 floorplan iterations before placement begins. Time spent improving the floorplan pays back 10× in placement and routing runtime savings. Changing a macro position after routing has started can invalidate days of work.
11. Common Floorplan Pitfalls
| Pitfall | Symptom | Fix |
|---|---|---|
| Macro island | Small standard cell pocket between macros with no routing escape | Move macros to edges; ensure every std-cell region has at least one open side |
| Narrow channel | Router fails to complete connections through macro channel | Increase channel to ≥10× cell height; reduce macro dimensions if possible |
| High-fanout net crossing chip | Clock or reset routing consumes many tracks, causing global congestion | Manually buffer high-fanout nets early; ensure clock root is central |
| Over-utilization | Placement fails or takes many hours; routing DRC cannot close | Increase core area (reduce utilization by 5–10%) |
| Macro misalignment to power grid | Power connections to macro require extra jogs; IR drop at macro corner | Snap macro to power stripe grid; adjust stripe pitch to match macro width |
| Clock pad far from PLL | Long clock input route → difficult timing closure on input path | Place clock pad closest to PLL location; PLL near center of die |
| Missing macro halo | DRC errors at macro boundary; router cannot access macro pins | Add halos of appropriate width for the process node |
12. EDA Tools for Floorplanning
| Tool | Vendor | Key strength |
|---|---|---|
| Innovus Implementation System | Cadence | Industry-leading PD tool; interactive floorplan GUI + scripting (TCL) |
| IC Compiler II (ICC2) | Synopsys | Very common in leading-edge nodes; tight STA integration with Primetime |
| Olympus-SoC | Siemens EDA | Popular in high-volume automotive and mobile designs |
| RedHawk / Voltus | Apache / Cadence | Early PDN IR drop and electromigration sign-off during floorplan |
| Synopsys StarRC / PrimeRail | Synopsys | Parasitic extraction and rail analysis for power sign-off |
13. FAQ
What is floorplanning in VLSI physical design?
Floorplanning is the first step of physical implementation. It takes a synthesized gate-level netlist and creates a spatial plan: defining die size, placing IO pads, fixing hard macro positions (SRAMs, PLLs, analog IP), building the power distribution network, and setting placement blockages. The floorplan quality determines timing, congestion, and power of the entire chip — errors here propagate through all subsequent steps.
What is core utilization and what should it be?
Core utilization = (total standard cell area) ÷ (core area) × 100%. Typical targets are 60–80%. Below 60% wastes silicon area and increases die cost. Above 80% causes routing congestion — the router runs out of tracks, timing closure becomes extremely difficult, and runtime explodes. For complex designs with many macros or high-frequency targets, 65–70% is safer.
Why must macros be placed at die edges and not in the center?
Hard macros are routing obstacles — no standard cell routes can pass through them. If placed in the center of the core, they fragment the standard cell area into isolated pockets with limited routing escape paths. This creates "macro islands" where routing resources are insufficient, leading to unroutable designs. Placing macros at edges or corners leaves a continuous open standard cell area in the center with full routing access from all sides.
What is power planning and why is it done during floorplanning?
Power planning creates the power distribution network (PDN) — the metal grid that delivers VDD and VSS to every cell on the chip. It is done during floorplanning because: 1) the PDN consumes routing resources on upper metal layers that must be reserved before signal routing begins; 2) PDN stripe placement must account for macro positions and blockages; 3) early IR drop analysis informs whether the floorplan is viable before investing time in placement and routing.
What is IR drop and why is it critical?
IR drop is the voltage loss from the power pad to a cell due to the resistance (R) of power grid metal and the current (I) drawn by cells — V_drop = I × R. If IR drop is too high, a cell receives VDD − V_drop instead of VDD, which slows its switching speed and can cause setup timing violations or even functional failures. The target is <5% of VDD. At 0.7V VDD (5nm node), <35 mV is the budget. Dynamic IR drop during simultaneous switching events is 2–3× static and must also be checked.
What is the difference between a hard macro and a soft macro?
A hard macro has a fixed, pre-characterized GDSII layout — its shape, size, and internal routing cannot change. Examples: SRAM compilers, ROM, PLL, analog blocks, IO pads, memory PHYs. The PD engineer places it as a fixed rectangle.
A soft macro is a synthesizable RTL block (a functional unit like a CPU core, FPU, or AES engine). It can be re-synthesized and re-placed for different aspect ratios or utilization targets — giving the floorplan engineer shape flexibility.
How many iterations does a typical floorplan go through?
A typical complex SoC floorplan goes through 3–10 iterations before placement begins, and may be revisited multiple times during the physical design cycle when timing or congestion problems are traced back to floorplan decisions. Each iteration involves adjusting macro positions, modifying power stripe pitch/width, changing die size, or rearranging IO pins — followed by re-running congestion and IR drop estimates. Getting the floorplan right early is the highest-ROI activity in physical design.