A chiplet package is only as good as the wires connecting the chiplets. Day 2 covers how die-to-die (D2D) interconnect actually works, the three metrics engineers optimize for, and the verified numbers from the UCIe 1.1 specification — the standard this course builds toward.
Die-to-Die Interconnect Is Not "Just a Wire"
Inside a monolithic die, wires connecting two blocks are essentially free — they're part of the same manufacturing step, extremely short, and extremely cheap in area and power. The moment you split a design into chiplets, every signal that used to cross an on-die wire now has to cross a package boundary: through a bump, across a substrate or interposer, and into another die's receiver. That boundary crossing has to solve three hard problems simultaneously: move enough data, don't burn too much power doing it, and reach far enough to physically connect the chiplets as placed.
The Three Metrics That Matter
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Bandwidth DensityData rate per millimeter of die edge (Tbps/mm) — edge length is limited, so density matters more than raw bandwidth
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Energy EfficiencyPicojoules per bit (pJ/bit) transferred — directly determines how much of your power budget the interconnect itself consumes
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ReachMaximum distance the link can drive reliably — depends entirely on the packaging technology, not just the transceiver design
These three trade off against each other. A link that reaches further generally needs more drive strength, which costs more energy per bit and more area per lane — which lowers bandwidth density. This is exactly why UCIe defines two distinct packaging categories instead of one.
Mainband and Sideband — Two Separate Channels
UCIe's Physical Layer carries two logically distinct channels:
Mainband — the actual high-speed data bus. Up to 64 transmit and 64 receive lanes per module for Advanced Package, or 16 and 16 for Standard Package, plus forwarded clock and framing signals.
Sideband — a separate, always-available low-speed channel used for parameter exchange, link negotiation, and register access — including during initial bring-up, before the mainband has even been trained.
This separation matters practically: if the high-speed mainband fails to train correctly, the sideband is still there to report status and enable debug, rather than the whole link going dark with no diagnostic path.
Link Training — Three Stages
Sideband detection & initialization — the two dies first establish the low-speed sideband link
Mainband training — parameter exchange over sideband, then lane repair and training of the high-speed mainband itself
Protocol parameter exchange — final negotiation over sideband before the link is handed off to the Protocol Layer above
UCIe Standard Package vs Advanced Package — Verified Numbers
UCIe 1.1 defines two packaging categories with genuinely different targets, not just two configuration options of the same thing:
Parameter
Standard Package
Advanced Package
Target substrate
Organic package substrate
Silicon interposer / bridge
Bump pitch
100–130 µm
25–55 µm
Link reach
Up to 25 mm (terminated)
Up to 2 mm (unterminated)
Energy efficiency target
0.5 pJ/bit
0.25 pJ/bit
Lanes per module
16 TX + 16 RX
64 TX + 64 RX
Bandwidth per module (example)
~0.25 Tbps at 16 GT/s per pin
~1 Tbps at 16 GT/s per pin
Aggregate bandwidth density
~0.9 Tbps/mm
~5.2 Tbps/mm
Figures per the UCIe 1.1 specification (released August 2023) and UCIe Consortium technical materials.
Worked Example — Where the Bandwidth Number Comes From
The "~1 Tbps per module" figure for Advanced Package isn't arbitrary — it comes directly from lane count × per-pin data rate:
Bandwidth calculation — Advanced Package module
64 lanes × 16 GT/s per lane = 1,024 Gbps ≈ 1 Tbps (per direction)
At the Standard Package's 16-lane width, the same per-pin rate gives:
16 lanes × 16 GT/s per lane = 256 Gbps ≈ 0.25 Tbps (per direction)
This is why Advanced Package delivers roughly 4× the per-module bandwidth of Standard Package at the same per-pin data rate — it simply has 4× the lane count, packed into a much finer bump pitch.
Per-Pin Data Rate Options
UCIe 1.1 defines a family of supported per-pin data rates: 4, 8, 12, 16, 24, and 32 GT/s. A designer picks a rate based on the reach required, the power budget available, and how much signal integrity margin the chosen packaging technology can support — a Standard Package link driving 25mm typically can't push the same per-pin rate as an Advanced Package link driving 2mm at the same power and error-rate target.
Why Reach and Bandwidth Density Trade Off
A finer bump pitch packs more lanes into the same edge length, directly raising bandwidth density — but finer pitch and shorter, unterminated links only work reliably over very short distances (a few millimeters), which is exactly what a silicon interposer or bridge provides. An organic substrate can't achieve that fine a pitch or that short a distance between arbitrary chiplets, so Standard Package trades bandwidth density for the ability to reach much further (up to 25mm) using a cheaper, more common packaging technology.
Die-to-Die Adapter Layer — What It Actually Does
Sitting above the Physical Layer, the Die-to-Die Adapter Layer handles:
Link management — bringing the link up, monitoring its health, handling power states
Protocol arbitration and negotiation — deciding which protocol (PCIe, CXL, or streaming) is active on the link and how it's multiplexed
Optional error correction — CRC-based error detection with a retry mechanism, so a bit error on the physical link doesn't necessarily become a data-corruption event at the protocol level
🎯 Day 2 Key Takeaways
Die-to-die interconnect must solve bandwidth, energy efficiency, and reach simultaneously — and these three trade off against each other
UCIe defines two distinct packaging categories: Standard Package (organic substrate, longer reach, lower density) and Advanced Package (interposer/bridge, shorter reach, much higher density)
Verified Advanced Package targets: 25–55µm bump pitch, 2mm reach, 0.25 pJ/bit, ~1 Tbps per module, ~5.2 Tbps/mm aggregate density
Verified Standard Package targets: 100–130µm bump pitch, 25mm reach, 0.5 pJ/bit, ~0.25 Tbps per module, ~0.9 Tbps/mm aggregate density
The UCIe stack has three layers: Physical (mainband + sideband, training/calibration), Die-to-Die Adapter (link management, arbitration, CRC+retry), and Protocol (PCIe/CXL/streaming)
Supported per-pin data rates: 4, 8, 12, 16, 24, and 32 GT/s
Frequently Asked Questions
What are the three metrics that matter most for die-to-die interconnect?
Bandwidth density (how much data rate you get per millimeter of die edge, since edge length is limited), energy efficiency measured in picojoules per bit (pJ/bit), and reach — the maximum distance the link can drive reliably, which depends on the packaging technology used.
What is the difference between UCIe Standard Package and Advanced Package?
Standard Package targets organic substrates with a 100-130 micron bump pitch, up to 25mm reach, and a 0.5 pJ/bit energy efficiency target. Advanced Package targets silicon interposers or bridges with a much finer 25-55 micron bump pitch, shorter 2mm reach, and a better 0.25 pJ/bit energy efficiency target, trading reach for much higher bandwidth density.
What are UCIe mainband and sideband channels?
The mainband is the high-speed data bus itself — up to 64 transmit and 64 receive lanes per module in Advanced Package, or 16 and 16 in Standard Package — plus forwarded clock and framing signals. The sideband is a separate, always-available low-speed channel used for parameter exchange, link negotiation, and register access, including during initial bring-up before the mainband is trained.
What are the three layers of the UCIe protocol stack?
Physical Layer (the electrical transmitter/receiver and sideband, plus link training and calibration logic), Die-to-Die Adapter Layer (link management, protocol arbitration, and optional CRC-based error correction with retry), and Protocol Layer (the actual protocol riding on top, such as PCIe, CXL, or a raw streaming mode).
What data rates does UCIe 1.1 support?
UCIe 1.1 defines per-pin data rates of 4, 8, 12, 16, 24, and 32 GT/s (gigatransfers per second), letting designers trade off raw per-pin speed against power and signal integrity margin depending on the packaging technology used.