Physical Design —
RTL to GDSII Flow

VLSI Physical Design — From Netlist to GDSII

Physical design is the stage of chip making where a logical description (a synthesised gate-level netlist) becomes an actual geometric layout that a foundry can manufacture. It is where timing, power, area and manufacturability all collide, and where many of the hardest, most valued engineering decisions in the industry are made.

The flow is a carefully ordered pipeline. After import and floorplanning, cells are placed, clocks are distributed, wires are routed, and the design is checked exhaustively against timing and physical rules. Each step constrains the next, so a weak floorplan can doom timing closure ten steps later — which is why experienced physical-design engineers think several stages ahead.

The main steps

• Floorplanning — deciding die size, block placement, power-grid structure and I/O.
• Placement — positioning standard cells to minimise wirelength and meet timing.
• Clock Tree Synthesis (CTS) — distributing the clock with low skew and controlled latency.
• Routing — connecting everything across metal layers without violations.
• Sign-off — static timing analysis, DRC, LVS, power and IR-drop checks before tape-out.

Physical design sits at the centre of the RTL-to-GDSII journey and demands fluency in static timing analysis, parasitics and the foundry rule deck. Explore the linked guides on floorplanning, clock trees and timing closure to go deeper, and try the interactive Sky130 floorplan tool to see the first step in action.