VLSI · Physical Design · RTL to GDSII

Physical Design —
RTL to GDSII Flow

Complete guide to VLSI Physical Design: every stage from netlist to chip layout — with diagrams, tool commands, and interview-ready explanations.

RTL → Synthesis → Floorplan → Placement → CTS → Routing → Sign-off → GDSII
RTL Verilog/VHDL Synthesis DC / Genus Floorplan Die · Macros · Power Placement Std cells · Timing CTS Clock Tree Routing Signal · Power Sign-off DRC · LVS · STA GDSII Tapeout Tools: Cadence Innovus · Synopsys ICC2 · OpenROAD · Calibre
Fig: Complete RTL-to-GDSII Physical Design flow — click any stage below to explore in depth
All Topics
Physical Design — Stage by Stage
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Stage 1
Floorplanning
Die size estimation, aspect ratio, IO placement, macro placement, power planning (rings, straps, rails), blockages, and utilization targets.
Die SizeMacro PlacementPower PlanningUtilization
Study Floorplanning →
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Stage 2
Placement
Standard cell placement — global vs detailed placement, timing-driven placement, congestion analysis, legalization, and placement optimization.
Global PlacementLegalizationTiming-DrivenCongestion
Study Placement →
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Stage 3
Clock Tree Synthesis (CTS)
Building the clock distribution network — clock tree topologies, skew minimization, insertion delay, useful skew, H-tree vs fishbone vs mesh.
Clock SkewInsertion DelayH-TreeUseful Skew
Study CTS →
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Stage 4
Routing
Global and detailed routing — signal routing, DRC rules, antenna effect, metal layer assignment, via optimization, and crosstalk handling.
Global RoutingDetailed RoutingAntenna EffectCrosstalk
Study Routing →
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Stage 5
Physical Sign-off
Pre-tapeout checks — DRC (design rule check), LVS (layout vs schematic), ERC, IR drop analysis, electromigration, and final STA sign-off.
DRCLVSIR DropElectromigration
Study Sign-off →