Phase 1 covered the interconnect standard. Phase 2 opens with the physical packaging technology that actually makes UCIe's Advanced Package numbers achievable. Day 6 explains what a silicon interposer really is, how TSMC's three CoWoS variants differ, and how Nvidia's Blackwell GPU uses the newest one to connect two dies at 10 TB/s.
"2.5D" describes a specific arrangement: multiple chiplets sit side by side on top of a shared interposer, which itself sits on the package substrate. The interposer is the thing doing the hard interconnect work between chiplets — the chiplets themselves aren't stacked directly on top of each other, which is what "3D" packaging means instead (Day 7). Think of 2.5D as chiplets on a shared, high-density wiring board that's itself part of the package, rather than a discrete PCB.
A silicon interposer is deliberately unglamorous: it's a piece of silicon fabricated on a mature, older process node (there's no benefit to using an expensive leading-edge node for something that does no computation), and it is entirely passive — no transistors doing logic, no active circuitry. Its only job is interconnect, achieved through two mechanisms:
Put simply: TSVs go through the interposer (vertical), RDL goes across the interposer (lateral). Together they let a chiplet's fine-pitch bumps connect both to its neighboring chiplet (via RDL) and down to the coarser package substrate (via TSV), without the chiplet itself ever needing bumps at two different pitches.
CoWoS (Chip-on-Wafer-on-Substrate) is TSMC's flagship 2.5D packaging technology, introduced in 2012 and now the dominant choice for AI and HPC silicon. It comes in three distinct variants that are not just configuration options — they trade off cost, yield, and performance differently:
| Variant | Interposer Type | Key Tradeoff | Typical Use |
|---|---|---|---|
| CoWoS-S | Single silicon interposer + TSVs | Best raw performance, but yield drops as interposer area grows | Nvidia H100, AMD MI300 — current AI/HPC mainstream |
| CoWoS-R | Organic RDL interposer (InFO fan-out, no silicon) | Lower cost, no TSV silicon needed, less bandwidth-critical | Networking products |
| CoWoS-L | Local Silicon Interconnect (LSI) bridges + RDL interposer | Preserves TSV-level performance while stitching past single-interposer size/yield limits | Nvidia Blackwell B100/B200 |
Variant details per TSMC technical disclosures and industry packaging coverage.
CoWoS-L is the most architecturally interesting of the three. Instead of one large monolithic silicon interposer (which, like a die, suffers yield problems as its area grows — the same yield-cliff logic from Day 1), CoWoS-L uses small local silicon interconnect (LSI) bridges embedded into a larger RDL interposer, stitching multiple segments together. This lets CoWoS-L build effective interposer areas over 3,000 mm² — far beyond what a single silicon interposer or even the reticle limit itself would allow — while still getting TSV-grade electrical performance exactly where the LSI bridges sit, right under the chiplet-to-chiplet connections that need it most.
This is the same idea from Day 1 applied one level up: just as splitting one large die into several chiplets sidesteps the reticle limit and the yield cliff, stitching several small silicon bridges into a larger RDL interposer sidesteps the same yield problem at the packaging level.
Nvidia's B100 and B200 GPUs were the first processors to use CoWoS-L in production. Blackwell connects two large compute chiplets using local silicon interconnect bridges and an RDL interposer, achieving 10 TB/s of chip-to-chip bandwidth between the two dies and packing 208 billion transistors into one package — more than 2.5× the transistor count of the prior Hopper generation's roughly 80 billion.
This is the practical payoff of everything covered so far in this course: two reticle-limited dies, joined by die-to-die interconnect running over a CoWoS-L 2.5D package, behaving as a single GPU to the software stack above them.
2.5D packaging isn't free of real engineering pain. Nvidia's early Blackwell production ramp ran into coefficient of thermal expansion (CTE) mismatch — the GPU chiplets, the silicon/RDL interposer, the LSI bridges, and the package substrate are different materials that expand and contract at different rates during manufacturing and thermal cycling. That mismatch caused warping severe enough to affect yield and reliability during the initial ramp. Advanced packaging solves the reticle limit and yield-cliff problems from Day 1 — but it introduces new thermomechanical problems that a monolithic die never had to deal with.