Phase 2 closes where every other challenge in this course ultimately gets paid for: power. Every chiplet needs current delivered to it with minimal resistive loss, through the same TSVs and interposers already covered — and the industry is now attacking the problem from two directions at once: smarter package-level power grids, and moving power delivery to the back of the die itself.
Day 6 introduced TSVs as the vertical interconnect carrying signal through a silicon interposer. The same physical structure also carries power — from the package substrate, up through interposer TSVs, into each chiplet's own on-die power grid. This means the power delivery network (PDN) design decisions made at the interposer level directly compete with signal routing for the same TSV budget, and getting this wrong shows up as IR drop — voltage sag under load that can push a chiplet's supply below the level it needs to operate reliably.
Published chiplet/interposer power-delivery co-design studies show that IR drop responds strongly to fairly modest design changes:
| Design change | Measured result |
|---|---|
| +5.52% interposer PDN occupancy, plus extra PDN grids | 27.17% improvement in overall IR drop |
| Bridge-chip design, 9 bundled 8µm-diameter TSVs | IR drop only ~1% higher than a standalone (non-chiplet) reference |
| Decoupling capacitors added to bridge-chip/interposer | Significant reduction in high-frequency supply ripple |
Figures per published chiplet/interposer power-delivery co-design research.
The takeaway from these numbers: a well-designed chiplet power grid doesn't have to cost you meaningfully more IR drop than a monolithic reference design — but you have to actually design for it, rather than treating the interposer's power grid as an afterthought behind the signal routing.
A passive interposer (Day 6) does nothing but carry TSVs and RDL wiring. An active interposer goes further, embedding integrated voltage regulators (IVRs) directly into the interposer itself, physically shortening the distance between the power supply and the power-hungry logic above it. One published study measured a 73.7% reduction in maximum IR drop compared to a passive interposer baseline — a dramatic result that reflects a simple physical truth: the further current has to travel through resistive metal before reaching the load, the more voltage it loses along the way. Put the regulation closer to the load, and that loss shrinks sharply.
Active interposers didn't appear from nowhere — they're the packaging-level evolution of an idea Intel first shipped inside a single die. FIVR (Fully Integrated Voltage Regulator), introduced with Intel's 4th-generation Core processors, packed 140 MHz multi-phase buck regulators directly onto the 22nm processor die itself, using on-die MIM capacitors and non-magnetic package trace inductors — flexible enough to power everything from 3W fanless tablets to 300W servers, and credited with 50%+ battery life improvements on mobile parts.
Intel later extended this idea to 3D-stacked chiplet systems: a 10-tile buck IVR using 3D-TSV-based, package-embedded inductors delivers power to chiplets stacked on top, demonstrating 37.6% higher efficiency than an equivalent low-dropout (LDO) regulator. The industry's more recent step is separating the regulator out entirely: rather than baking a FIVR into the main die (where analog circuitry doesn't scale with process node the way logic does, eating disproportionate die area), modern designs increasingly implement the voltage regulator as its own dedicated chiplet — the natural conclusion of treating power delivery as a first-class chiplet in its own right, alongside compute, memory, and I/O.
Deep trench capacitors round out this picture — capacitor structures embedded directly in the package substrate (or in a silicon interposer, as demonstrated for CoWoS heterogeneous integration) provide the decoupling capacitance a switched-capacitor voltage regulator needs for high efficiency, high power density, and fast transient response, without consuming precious die-level area.
A parallel, complementary industry shift moves power delivery off the frontside of the die entirely. Backside Power Delivery Networks (BSPDN) relocate the entire power grid to the wafer's backside, connecting to transistors through dedicated vias, while freeing the frontside exclusively for denser signal routing — the same "get the two jobs out of each other's way" logic that motivates separating power and signal at the interposer level, just applied one layer down, inside the die itself.
Intel's own reported results for 18A PowerVia in production: roughly 30% IR-drop reduction, a 6% frequency uplift, and 5–10% better standard cell utilization — utilization improves because power routing no longer competes with signal routing for frontside metal layers. Separately, broader backside-power-delivery research across sub-5nm nodes has reported around 10% IR-drop reduction as a more general figure, underscoring that Intel's specific implementation and results are on the strong end of what backside power delivery can achieve.
Two techniques solving one problem at two scales: active interposers and optimized package-level PDN attack IR drop at the chiplet-to-package boundary. Backside power delivery attacks the same fundamental problem — resistive loss between power source and transistor — at the within-die boundary. A cutting-edge chiplet package increasingly uses both simultaneously.