Twelve days of theory now meet the products actually shipping. Day 1 name-dropped these products; Day 13 goes back with everything learned since — packaging technology, bandwidth numbers, and design tradeoffs — to explain exactly what each company built and why.
AMD's MI300X combines CPU, GPU, and HBM memory chiplets into a single AI/HPC accelerator package, built on CoWoS-S (Day 6) — TSMC's single-silicon-interposer 2.5D technology, currently the mainstream choice for high-performance accelerators alongside Nvidia's H100. Recall from Day 8 that a design this complex, with roughly a dozen chiplets, faces real yield-multiplication math: even at a strong 98% known-good-die yield per chiplet, a 12-chiplet package composite yield lands around 78.5% — which is exactly why rigorous pre-bond KGD testing (Day 8) matters most for products at this scale.
| Product | Chiplet Count | Packaging | Significance |
|---|---|---|---|
| Ponte Vecchio (Xe-HPC) | 47 chiplets | Mix of Foveros (3D) and EMIB (2.5D) | One of the most aggressive chiplet counts shipped in a single product; combines both major Intel packaging technologies in one part |
| Meteor Lake (2023) | Multiple tiles | Foveros 3D stacking | Intel's first chiplet-based consumer SoC — compute, graphics, SoC, and I/O tiles combined into one package |
These two products make different bets on purpose: Ponte Vecchio is a data-center part where extreme chiplet count and mixed packaging technology are worth the complexity for maximum performance. Meteor Lake is a consumer part where Foveros 3D stacking lets Intel mix process nodes across tiles (recall Day 1's "best node per function" argument) without the cost structure of a data-center-grade package.
Apple's UltraFusion interconnect, used identically in both the M1 Ultra and M2 Ultra, joins two full M-series dies (M1 Max or M2 Max) into one package via TSMC's CoWoS-S. Unlike AMD or Intel's heterogeneous chiplet mixes, this is a homogeneous case — two identical dies fused together — which makes it one of the cleanest real-world illustrations of Day 2's bandwidth-density concepts: over 10,000 signals across the interposer is only achievable because CoWoS-S's silicon interposer supports far finer bump pitch and higher lane counts than any board-level connector ever could.
AMD, Intel, and Apple design and sell their own chips. A fourth, increasingly important category doesn't: hyperscalers (Google, Amazon, Microsoft, Meta, OpenAI) designing custom chiplet-based silicon for their own data centers, typically partnering with Broadcom or Marvell to actually implement and package the design — between them, Broadcom and Marvell enable over 80% of hyperscaler custom AI silicon. The accurate framing is that hyperscalers design chips in partnership with these firms, rather than building them from scratch alone.
| Chip | Company | Verified Specs |
|---|---|---|
| TPU v7 "Ironwood" | Google (built with Broadcom) | 4,614 FP8 TFLOPS, 192GB HBM3E, 7.37 TB/s bandwidth — announced April 2025 |
| Trainium3 | Amazon (AWS's first 3nm chip) | 2.517 PFLOPS FP8, 144GB HBM3E, 4.9 TB/s bandwidth |
| Trainium4 | Amazon (announced Dec 2025) | Targeting 3× FP8 / 6× FP4 throughput and 4× memory bandwidth over Trainium3, ~288GB memory, late 2026/early 2027 availability |
Broadcom's own packaging push reinforces the pattern: in February 2026, Broadcom announced its first 2nm custom compute SoC, built using a chiplet architecture on a jointly-developed-with-TSMC 3.5D packaging platform (branded XDSiP) using face-to-face bonding to stack memory and compute at very high density — the same fundamental toolkit (Days 6-7) applied at a scale most consumers never see, since these parts never ship as retail products.
Despite different products, different chiplet counts, and different packaging technology choices, all three companies are solving the exact same problem from Day 1: the reticle limit and yield cliff make a single, larger monolithic die uneconomical or physically impossible at these performance targets. AMD and Apple reach for the same base packaging technology (CoWoS-S) for different products; Intel mixes two of its own technologies (EMIB, Foveros) depending on whether a product needs 2.5D side-by-side placement or 3D vertical stacking. The engineering path differs; the underlying economic driver is identical.