Every digital chip with multiple clock domains faces a single, unavoidable problem: metastability. An asynchronous input can arrive at a flip-flop just as the clock edge triggers, violating setup and hold times. The output becomes unpredictable — neither 0 nor 1, but something in between. This is not a design flaw. It is a fundamental physics problem that every chip designer must solve.
A flip-flop is a bistable device — it has two stable states: 0 and 1. When the input changes during the clock edge, the flip-flop briefly enters an unstable, intermediate voltage level. Normally, this happens fast enough that we never see it — the output settles to 0 or 1 before we read it.
But when an asynchronous input violates setup or hold time, the flip-flop output can settle to a voltage in the analog range — not 0, not 1, but something in between. This metastable state will eventually decay to either 0 or 1, but the timing is unpredictable. It might take nanoseconds or microseconds.
A metastable output is invalid logic. If downstream logic reads it before it settles, the result is undefined. The output might resolve to 0 in one chip, to 1 in another identical chip. It might change depending on temperature, voltage, or process variation. This creates non-deterministic bugs that appear randomly in the field and are nearly impossible to debug.
Whenever an asynchronous signal crosses from one clock domain to another without synchronization. Example:
req in clock domain A changes statereq change aligns with clock B's edgeAt the transistor level, a flip-flop is two cross-coupled gates. When setup/hold is violated, both transistors can be partially on, creating an unstable equilibrium. The output voltage sits between VDD and GND, valid as neither 0 nor 1.
This metastable state decays exponentially — the flip-flop eventually settles to 0 or 1. But the settling time is random and depends on:
You might think: "Just give the async input enough setup/hold time with careful routing and constraints."
This doesn't work.
You cannot guarantee an asynchronous signal from a different clock domain will align with your flip-flop clock. The two clocks are independent — their edges have no fixed relationship. Over time, the timing relationship drifts. Eventually, a rising edge of req will arrive just as the clock edge samples it, violating setup time.
The only solution is to synchronize — accept that metastability can happen, but add circuits that detect it and allow time to resolve before using the data.
| What happens | Outcome |
|---|---|
| Metastable output propagates through logic | Invalid voltage levels in combinational paths |
| Downstream logic interprets metastable state | Random 0 or 1 depending on circuit threshold |
| Corruption enters state machine or counter | State machine goes to invalid state |
| Corruption reaches system output | Silent data corruption or system crash |
| Bug occurs randomly (depends on PVT) | Passes simulation, fails in field |
This is not a theoretical problem. Intel's famous FDIV bug (1994) was not caused by metastability, but modern multi-clock chips fail regularly due to CDC violations caught too late. Qualcomm's 2021 security issues involved clock domain crossing bugs. Every major chip project has at least one CDC-related incident. This is why CDC verification is a critical job skill and why CDC violations must be caught in design review and formal verification, not in the field.
When an asynchronous input violates a flip-flop's setup/hold time, the output settles to an invalid voltage between 0 and 1, eventually resolving unpredictably to either 0 or 1.
The settling time depends on how close to the clock edge the setup violation occurs, and varies with process, temperature, and voltage. This means the output resolves non-deterministically.
No. Asynchronous signals are guaranteed to violate setup/hold time eventually. The solution is synchronizers that accept metastability and allow time to resolve.
Silent data corruption in the field. Bugs that pass simulation but fail at customer sites. This is why CDC is a critical job skill.