RISC-V from Scratch

We're going to build a working RISC-V processor — together with Claude writing and optimizing every line of Verilog. From the instruction set to a single-cycle core, then a pipelined, optimized CPU you can run in your browser. Every module's code is copy- and download-ready.

▶ Start with Day 1 — The Plan

Most courses describe a CPU. This one builds one. Step by step, you'll assemble a real RV32I RISC-V processor in Verilog — register file, ALU, control unit, datapath — until it executes an actual program. Then we'll optimize it: pipeline it, add forwarding and hazard handling, CSRs, and I/O. Claude designs and writes the RTL, explains every decision, and you can copy or download each module and test it live in our online Verilog simulator. No prior CPU-design experience needed — just basic Verilog.

PHASE 1

The RISC-V ISA

Day 1Introduction & the plan — what we're building & howLive Day 2RISC-V registers & the RV32I baseLive Day 3Instruction formats — R, I, S, B, U, JLive Day 4The RV32I instruction set in fullLive Day 5Memory, the stack & calling conventionLive Day 6Writing & running RISC-V assemblyLive

PHASE 2

Build a Single-Cycle Core (Verilog)

Day 7Datapath overview — fetch · decode · executeLive Day 8Program counter & instruction memoryLive Day 9The register fileLive Day 10The ALULive Day 11Immediate generation & the control unitLive Day 12R-type & I-type datapathLive Day 13Loads & storesLive Day 14Branches & jumpsLive Day 15🎉 Your first working RISC-V core — runs a program!Live

PHASE 3

Pipeline & Optimize It

Day 16Testbench & simulationLive Day 17The 5-stage pipelineLive Day 18Data hazards & forwardingLive Day 19Control hazards & branch handlingLive Day 20Load-use stalls & the hazard unitLive

PHASE 4

Advanced & Real Hardware

Day 21CSRs, traps & exceptionsLive Day 22Memory-mapped I/O — a UARTLive Day 23The M-extension — multiply & divideLive Day 24Run your CPU on an FPGALive Day 25Caches & the road to Linux-capableLive

New lessons publish regularly. Every module is copy/download-ready and runnable in the Verilog simulator. Also see ARM from Scratch, FPGA from Scratch and SHAKTI.