Why Reset is Hard
In a multi-clock chip, all flip-flops must reset synchronously. But a global async reset signal crossing clock domains violates setup/hold, causing metastability in every domain.
Synchronizing Reset
// Global async reset
input async_reset;
// Synchronizers in each clock domain
sync_2ff reset_sync_a (.in(async_reset), .out(reset_a), .clk(clk_a));
sync_2ff reset_sync_b (.in(async_reset), .out(reset_b), .clk(clk_b));
// Use synchronized reset in each domain
always @(posedge clk_a or negedge reset_a) begin
if (!reset_a) counter_a <= 0;
else counter_a <= counter_a + 1;
endAssertion for Reset Safety
// Verify reset propagation
assert property (@(posedge clk_b) async_reset |-> ##3 reset_b);
assert property (@(posedge clk_a) async_reset |-> ##3 reset_a);Key Takeaways
- ✅ Reset must sync to every clock domain
- ✅ Never use async reset in multiple domains
- ✅ Add 2-3 cycles delay for synchronization
Day 8: Arbiters and control + data CDC.