Design Review Questions
- ☐ Have you identified all clock domains?
- ☐ Have you mapped all cross-domain signal paths?
- ☐ Is every async input synchronized (2+ FF)?
- ☐ Are multi-bit buses using Gray code or handshake?
- ☐ Is reset synchronized to each clock domain?
- ☐ Are pulse signals using pulse synchronizers or stretchers?
- ☐ Does every handshake have request-acknowledge pairing?
- ☐ Are arbiters properly CDC'ed?
- ☐ Have you run formal CDC verification (SpyGlass, etc.)?
- ☐ Have you simulated with non-integer clock ratios?
- ☐ Have you reviewed corner cases (slow/fast PVT)?
- ☐ Is CDC documented in architecture spec?
Red Flags
⚠️ Async signal used directly (no synchronizer)
⚠️ Single-flop synchronizer
⚠️ Gray code on non-pointer (won't work)
⚠️ Reset without synchronization
⚠️ Back-to-back synchronizers (2-cycle latency)
⚠️ Combinational logic between sync stages (adds delay)
⚠️ Single-flop synchronizer
⚠️ Gray code on non-pointer (won't work)
⚠️ Reset without synchronization
⚠️ Back-to-back synchronizers (2-cycle latency)
⚠️ Combinational logic between sync stages (adds delay)
Day 15: Real-world case studies and lessons learned.