The coherent interconnect that lets CPUs, accelerators, and memory pools share memory across a link — breaking the AI memory wall through pooling and disaggregation. The most talked-about data-center technology of the decade, taught in depth and free.
▶ Start with Day 1 — What is CXL?
Who this is for: Data-center architects, VLSI and SoC engineers, systems-software developers, and anyone trying to understand why "memory disaggregation" and "CXL" appear in nearly every AI-infrastructure discussion today. No prior CXL experience needed — but a working grasp of PCIe and CPU memory helps.
What you'll learn: The complete CXL story — from the coherent-interconnect fundamentals and the three sub-protocols, through the spec evolution from CXL 1.1 to 4.0, all the way to memory pooling, disaggregation, the software tiering stack, and the real products shipping today. Every technical claim in this course is verified against primary sources before publishing.
A CPU can only physically attach so much memory to its own DIMM slots. Meanwhile, in real data centers, an average of ~6% of memory is "stranded" — allocated to a socket but unused because that socket's cores are already fully scheduled — rising to as much as 25% as VM and container density increases. You're paying for DRAM that no workload can reach. At the same time, large AI models are hard-limited by memory capacity and bandwidth: the "memory wall." CXL attacks both problems at once, by making memory a shared, coherent, expandable resource reachable over a link rather than a fixed quantity bolted to one CPU.
Stranded-memory figures per published data-center memory utilization studies.
CXL is an open, cache-coherent interconnect standard that runs on top of the PCIe physical layer. It reuses PCIe's electrical signaling and connectors, then layers cache-coherent protocols on top — which is precisely what plain PCIe cannot do. That coherence is the whole point: it lets a device and a host agree on the state of shared memory in hardware, so memory attached to a device can behave, to software, like memory attached to the CPU itself.
CXL.ioConfiguration & I/ODiscovery, enumeration, register access, DMA — functionally similar to PCIe, and the mandatory baseline every CXL device supports.CXL.cacheDevice caches host memoryLets an accelerator coherently cache the host's memory, so it can work on shared data without constant round-trips.CXL.memHost accesses device memoryLets the CPU access memory attached to a device — the basis of memory expanders and pooling.Which sub-protocols a device speaks defines what kind of CXL device it is:
| Device Type | Sub-Protocols | What It Is |
|---|---|---|
| Type 1 | CXL.io + CXL.cache | Accelerator with a cache but no host-attached memory (e.g. a SmartNIC or coherent accelerator) |
| Type 2 | CXL.io + CXL.cache + CXL.mem | Accelerator with its own directly-attached memory, kept coherent with the host (e.g. a GPU/accelerator with local memory) |
| Type 3 | CXL.io + CXL.mem | Memory expander — presents DRAM or persistent memory to the CPU over CXL.mem. The workhorse of memory expansion and pooling. |
CXL's power grew dramatically across versions. Each generation rides a newer PCIe physical layer and adds fundamentally new capabilities, not just more speed:
| Version | Released | PCIe Base / Speed | Headline Capability |
|---|---|---|---|
| CXL 1.0 / 1.1 | 2019 | PCIe 5.0 / 32 GT/s | Memory expansion, coherent accelerator caching, device-host memory sharing |
| CXL 2.0 | 2022 | PCIe 5.0 / 32 GT/s | Switching, hot-plug, memory pooling, and IDE (link encryption & integrity) |
| CXL 3.0 | 2023 | PCIe 6.0 / 64 GT/s (PAM4) | Fabric-level memory sharing (multiple hosts, one region, coherent), multi-level switching, 256B flit |
| CXL 3.1 | 2023 | PCIe 6.0 / 64 GT/s | Fabric scale-out via Port-Based Routing (PBR), Trusted-Execution security (TSP) for confidential computing |
| CXL 4.0 | Nov 2025 | PCIe 7.0 / 128 GT/s | Bandwidth doubling, bundled ports supporting up to 1.5 TB/s connections |
Versions, dates, and PCIe base speeds per CXL Consortium specifications and public disclosures.
The single most important distinction to remember: CXL 2.0 introduced pooling — a memory region can be dynamically reassigned between hosts, but only one host owns it at a time. CXL 3.0 introduced sharing — multiple hosts can coherently access the same region simultaneously, with hardware maintaining coherence. That jump from pooling to sharing is what turns CXL from a memory-expansion feature into a genuine memory fabric.
Pair with the Chiplets & UCIe Course for the complete picture of how modern chips and memory fabrics connect — UCIe links chiplets inside the package, CXL links memory and accelerators across the system.