Day 3 ended with a preview: a CXL device's "type" is simply which sub-protocols it implements. Day 4 makes that concrete. The three device types are the single most-referenced classification in all of CXL — every product, every spec discussion, every deployment is framed around them. By the end of this lesson you'll instantly know what a "Type 3 device" can and can't do.
There's an elegant logic here. From Day 3, the three sub-protocols are CXL.io (mandatory), CXL.cache (device caches host memory), and CXL.mem (host accesses device memory). The three device types are just the three meaningful combinations of these:
A Type 1 device implements a fully coherent cache but has no host-managed device memory of its own. It uses coherency semantics (via CXL.cache) alongside PCIe-style DMA (via CXL.io). Because it has no local memory to expose, it only ever reaches into host memory — never the reverse.
Classic example: the SmartNIC. A network accelerator that needs to coherently touch host memory — inspecting packets, updating data structures, participating in host data with a consistent view — benefits enormously from a coherent cache, but has no reason to expose memory of its own back to the host. Type 1 is exactly that shape. These devices may also need to implement a custom ordering model on top of the coherent cache, depending on their workload.
A Type 2 device uses all three protocols. It has an (optional) coherent cache and its own local memory that can be mapped into the host's coherent address space. This is the only device type that operates in both directions — it caches host memory (CXL.cache) and exposes its own memory to the host (CXL.mem).
Classic examples: GPUs and FPGAs with local memory. These accelerators have large, high-bandwidth local memory (e.g. GDDR or HBM) that traditionally lived in a completely separate address space from the CPU, forcing explicit copies back and forth. As a Type 2 CXL device, that local memory can be partly mapped into the host's cacheable system memory, enabling unified memory access — the CPU and accelerator working on the same data without manual copying. This is one of the most powerful things CXL enables, and it's unique to Type 2.
A Type 3 device has host-managed device memory but no coherent cache. Its entire purpose is to be memory the host reaches into via CXL.mem. It deliberately omits CXL.cache — a pure memory expander has nothing to cache from the host.
This is the workhorse of the CXL memory story. Type 3 devices provide memory capacity and bandwidth expansion — presenting additional DRAM or persistent memory to the host beyond what fits in the CPU's own DIMM slots. They can connect different memory types and even support multiple memory tiers attached to a single device. Every CXL memory-expansion, pooling, and disaggregation deployment (Days 11–13) is built on Type 3 devices, precisely because they're simple, cheap, and purpose-built to be memory.
Why omitting CXL.cache is a feature, not a limitation: leaving out coherent-caching logic makes a Type 3 device dramatically simpler and cheaper to build than a Type 2. Since a memory expander genuinely has nothing to cache from the host, that logic would be dead weight. This simplicity is a big part of why Type 3 memory expanders were the first CXL devices to reach real volume in the market.
The phrase "host-managed device memory" (HDM) keeps appearing — it's worth defining precisely. HDM is memory physically attached to a CXL device but mapped into the host's address space, so the host can access it with ordinary loads and stores. In its simplest form, the host is responsible for managing that memory's coherence.
HDM is exactly what makes device-attached memory behave like part of the system's own memory rather than a separate island reachable only through explicit I/O. How the coherence of that HDM is actually managed — whether the host tracks everything, or the device takes a more active role, and the bias modes that govern it — is the entire subject of Day 5.
| Type | Protocols | Cache? | Device Memory? | Typical Example |
|---|---|---|---|---|
| Type 1 | io + cache | Yes | No | SmartNIC, I/O accelerator |
| Type 2 | io + cache + mem | Yes (optional) | Yes (HDM) | GPU, FPGA with local memory |
| Type 3 | io + mem | No | Yes (HDM) | DRAM / persistent-memory expander |