What is quantization error in an ADC?

Quantization error is the difference between the actual analog input and the nearest representable digital level. For an N-bit ADC with reference voltage Vref, the LSB (least significant bit) step size is Vref / 2^N. The worst-case quantization error is ±0.5 LSB. This error is unavoidable — it is the fundamental precision limit of any ADC. Higher resolution (more bits) reduces the LSB size and thus the quantization error.

What is the difference between Flash ADC and SAR ADC?

A Flash ADC uses 2^N − 1 parallel comparators to convert in a single clock cycle — extremely fast (GHz) but power-hungry and only practical up to ~8 bits (255 comparators). A SAR (Successive Approximation Register) ADC uses a binary search algorithm with one comparator: it takes N clock cycles to produce an N-bit result, trying the MSB first and working down. SAR ADCs dominate for 12–18 bit, 1–100 MSPS applications because they balance speed, resolution, and power.

What is a Sigma-Delta ADC?

A Sigma-Delta (ΣΔ) ADC uses oversampling and noise shaping to achieve very high resolution (16–24 bits) at low to moderate speeds. It samples the input at many times the Nyquist rate using a 1-bit or low-bit quantizer, then a digital decimation filter averages the bitstream to produce high-resolution output. The noise shaping pushes quantization noise to high frequencies where it is filtered out. Sigma-Delta ADCs are standard in audio (CD quality = 16-bit at 44.1kHz) and precision measurement.

What does ENOB mean in ADC specifications?

ENOB (Effective Number of Bits) is the real-world resolution of an ADC after accounting for noise, distortion, and non-linearity — as opposed to the nominal bit count. Formula: ENOB = (SINAD − 1.76) / 6.02. An ideal N-bit ADC has ENOB = N. A real 12-bit ADC might have ENOB of 10.5 bits due to thermal noise and harmonic distortion. ENOB is the most honest single-number figure of merit for ADC quality.

What is INL and DNL in an ADC?

DNL (Differential Non-Linearity) measures how much each individual code step deviates from the ideal 1 LSB step. DNL = −1 LSB means a missing code (that output level is never produced). INL (Integral Non-Linearity) measures the cumulative deviation of the ADC transfer function from a straight line — the worst-case INL across all codes. Both are specified in LSBs. A high-quality ADC has |INL| < 0.5 LSB and |DNL| < 0.5 LSB (no missing codes guaranteed).

How is an ADC modeled in Verilog?

An ADC is typically modeled behaviorally in Verilog for simulation — the actual ADC is a mixed-signal block that can't be synthesized in pure digital RTL. A behavioral model takes a real-valued input (using SystemVerilog real type or a scaled integer) and produces an N-bit quantized digital code: dout = $rtoi(vin / vref * (2**N)). For SAR ADC control logic, you can write synthesizable Verilog that drives the SAR FSM, DAC feedback, and comparator, which is the digital portion of a SAR ADC ASIC.

ADC – Analog to Digital Converter Explained

Q: What is an ADC and how does it work?

An ADC (Analog-to-Digital Converter) converts a continuous analog voltage into a discrete digital code. The process has three steps: sampling (capturing the analog value at regular intervals), quantization (mapping the sampled value to the nearest discrete level), and encoding (expressing that level as an N-bit binary number). The Nyquist theorem requires the sampling rate to be at least twice the highest frequency of interest to avoid aliasing.

Q: How is an ADC modeled in Verilog?

An ADC is typically modeled behaviorally in Verilog for simulation — the actual ADC is a mixed-signal block that can't be synthesized in pure digital RTL. A behavioral model takes a real-valued input (using SystemVerilog real type or a scaled integer) and produces an N-bit quantized digital code: dout = $rtoi(vin / vref * (2**N)). For SAR ADC control logic, you can write synthesizable Verilog that drives the SAR FSM, DAC feedback, and comparator, which is the digital portion of a SAR ADC ASIC.

Architecture Overview

ADC Signal Chain Block Diagram

Core Formulas

Resolution, SNR & LSB

LSB Size

LSB = V_ref / 2^N

Voltage per step. 12-bit at 3.3V → LSB = 3.3/4096 ≈ 0.806mV.

SNR (ideal)

SNR = 6.02N + 1.76 dB

Each extra bit adds ~6dB SNR. 12-bit ideal SNR = 74dB.

ENOB

ENOB = (SINAD − 1.76) / 6.02

Real-world effective bits after noise & distortion. Always ≤ N.

Nyquist Rate

f_s ≥ 2 × f_max

Sample at least twice the highest input frequency to avoid aliasing.

Quantization Error

ε = ±½ LSB

Worst-case rounding error per conversion. Irreducible for any ADC.

Output Code

D = floor(V_in / V_ref × 2^N)

Integer digital output. Saturates at 2^N−1 when V_in = V_ref.

Architectures

ADC Types Compared

Type	Speed	Resolution	Power	How It Works	Applications
Flash	GHz	4–8 bit	Very high	2^N−1 comparators in parallel — all levels checked simultaneously	Oscilloscopes, SerDes CDR
SAR	1–100 MSPS	8–18 bit	Low	Binary search: N decisions per sample using one comparator + DAC	MCUs, data acquisition, IoT sensors
Sigma-Delta (ΣΔ)	1 Hz–10 MSPS	16–32 bit	Moderate	1-bit oversampling + noise shaping + decimation filter	Audio codecs, precision instrumentation, weighing scales
Pipeline	10–500 MSPS	8–16 bit	Moderate	Cascaded stages each resolving a few bits; adds latency but high throughput	Cable modems, imaging, software radio
Dual-Slope	Very slow (Hz)	16–24 bit	Low	Integrates Vin for fixed time, then de-integrates reference — ratio is code	DMMs, benchtop meters, EEG

SAR ADC — Most Common Architecture

How SAR Works: Binary Search

The SAR (Successive Approximation Register) ADC is the workhorse of precision data conversion. For an N-bit conversion it makes exactly N comparator decisions, one per clock cycle:

Step 1 (MSB): Set DAC to Vref/2. If Vin > Vref/2 → bit N-1 = 1, else 0.
Step 2: Set DAC to previous result ± Vref/4. Compare again → bit N-2.
… Repeat, halving the search interval each step.
Step N (LSB): Final comparison gives the least significant bit.

Result: N-bit resolution in N clock cycles with only 1 comparator. This is why SAR ADCs dominate in power-sensitive designs — the architecture is inherently efficient.

Example (4-bit, Vref=16V, Vin=9.5V):
Trial 8V → 9.5>8 → 1 | Trial 12V → 9.5<12 → 0 | Trial 10V → 9.5<10 → 0 | Trial 9V → 9.5>9 → 1
Result: 1001 = 9 × (16/16) = 9V (error = 0.5V = ½ LSB ✓)

Interactive Simulator

ADC Quantization Demo

V_in 1.65V

0VV_ref=3.3V

Resolution 8-bit

Digital Output (MSB → LSB)

Digital Code

128

Hex

0x80

Reconstructed V

1.6435V

Quant. Error

+0.006V

LSB Size

12.9mV

Ideal SNR

49.9dB

Verilog RTL

ADC Models in Verilog

Behavioral ADC (Simulation Model)

// Behavioral ADC model for simulation
// Uses real-valued input — not synthesizable
module adc_model #(
  parameter N    = 12,          // bit resolution
  parameter real VREF = 3.3     // reference voltage
)(
  input  wire        clk,
  input  wire        rst_n,
  input  real        vin,       // analog input (simulation only)
  output reg  [N-1:0] dout,      // digital output code
  output reg         valid      // conversion complete
);
  real clipped;

  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      dout  <= '0;
      valid <= 1'b0;
    end else begin
      // Clip input to [0, VREF]
      clipped = (vin < 0.0) ? 0.0 : (vin > VREF) ? VREF : vin;
      // Quantize: floor(vin/vref * 2^N)
      dout  <= $rtoi(clipped / VREF * (1 << N));
      valid <= 1'b1;
    end
  end
endmodule

SAR ADC Control Logic (Synthesizable)

// SAR ADC digital control — drives external DAC + comparator
// N-bit result in N clock cycles after start pulse
module sar_ctrl #(
  parameter N = 12
)(
  input  wire        clk,
  input  wire        rst_n,
  input  wire        start,     // begin conversion
  input  wire        cmp_out,   // comparator: 1 = Vin > Vdac
  output reg  [N-1:0] dac_code,  // drives the internal DAC
  output reg  [N-1:0] result,    // final N-bit ADC output
  output reg         done       // conversion complete
);
  reg [$clog2(N)-1:0] bit_idx;  // current bit being tested
  reg                 busy;

  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      dac_code <= '0; result <= '0;
      done <= 0; busy <= 0; bit_idx <= N-1;
    end else if (start && !busy) begin
      // Start: set MSB trial, clear result
      result   <= '0;
      dac_code <= (1 << (N-1));
      bit_idx  <= N-2;
      busy     <= 1;
      done     <= 0;
    end else if (busy) begin
      // Keep or clear the bit we just tested
      result <= cmp_out ? (result | dac_code) : result;

      if (bit_idx == 0) begin
        // Last bit — latch and signal done
        dac_code <= (1 << 0);
        busy     <= 0;
        done     <= 1;
      end else begin
        dac_code <= (1 << bit_idx);
        bit_idx  <= bit_idx - 1;
      end
    end else begin
      done <= 0;
    end
  end
endmodule

Flash ADC Concept (4-bit)

// Flash ADC: 2^N-1 comparators, thermometer → binary encoder
// For 4-bit: 15 comparators, 1 cycle latency
module flash_adc4 (
  input  wire [7:0] vin_scaled,   // 0-255 maps to 0-Vref (scaled input)
  output reg  [3:0] dout          // 4-bit digital output
);
  wire [14:0] therm;  // thermometer code (15 comparators)

  // Comparators: level[k] = k * (256/16)
  genvar k;
  generate
    for (k=0; k<15; k=k+1)
      assign therm[k] = (vin_scaled > (k+1)*16);
  endgenerate

  // Priority encoder: thermometer → binary
  always @(*) begin
    casez (therm)
      15'b000_0000_0000_0000: dout = 4'd0;
      15'b000_0000_0000_0001: dout = 4'd1;
      15'b000_0000_0000_0011: dout = 4'd2;
      15'b000_0000_0000_0111: dout = 4'd3;
      15'b000_0000_0000_1111: dout = 4'd4;
      15'b000_0000_0001_1111: dout = 4'd5;
      15'b000_0000_0011_1111: dout = 4'd6;
      15'b000_0000_0111_1111: dout = 4'd7;
      15'b000_0000_1111_1111: dout = 4'd8;
      15'b000_0001_1111_1111: dout = 4'd9;
      15'b000_0011_1111_1111: dout = 4'd10;
      15'b000_0111_1111_1111: dout = 4'd11;
      15'b000_1111_1111_1111: dout = 4'd12;
      15'b001_1111_1111_1111: dout = 4'd13;
      15'b011_1111_1111_1111: dout = 4'd14;
      default:                dout = 4'd15;
    endcase
  end
endmodule

FAQ

Frequently Asked Questions

What is an ADC and how does it work?

An ADC converts a continuous analog voltage into a discrete N-bit digital code via three steps: sampling (capturing Vin at regular intervals), quantization (rounding to the nearest of 2^N levels), and encoding (representing that level as binary). The Nyquist theorem requires f_s ≥ 2 × f_max to prevent aliasing.

What is quantization error?

Quantization error is the irreducible rounding error from mapping a continuous value to the nearest discrete level. Worst-case = ±½ LSB. For a 12-bit ADC at 3.3V: LSB = 0.806mV, so worst error = ±0.403mV. More bits → smaller LSB → smaller error.

Flash vs SAR ADC — which to choose?

Flash: single-cycle conversion at GHz speeds, but 2^N−1 comparators make it impractical above 8 bits. SAR: N cycles for N bits, one comparator, low power — the best choice for 10–18 bit at up to 100 MSPS. For audio (16–24 bit at ≤384kHz), use Sigma-Delta.

What is ENOB?

ENOB (Effective Number of Bits) = (SINAD − 1.76) / 6.02. It measures real-world resolution after noise and distortion. A 16-bit ADC might have ENOB of 13.5 bits — the actual useful precision. ENOB is always ≤ nominal N and is the most honest spec for ADC quality.

What are INL and DNL?

DNL measures deviation of each code step from the ideal 1 LSB. DNL = −1 LSB means a missing code. INL measures the worst-case cumulative deviation of the full transfer curve from a straight line. Both in LSBs; ideally |INL|, |DNL| < 0.5 LSB for no missing codes.

How does Sigma-Delta ADC achieve high resolution?

ΣΔ uses a 1-bit quantizer running at many times (OSR = 64–512×) the Nyquist rate, plus noise shaping which pushes quantization noise to high frequencies. A digital decimation filter then averages the bitstream, reducing noise and increasing effective resolution. 24-bit ENOB is achievable at audio rates.

Analog-to-Digital Converter (ADC)