Digital-to-Analog Converter (DAC)

// Behavioral DAC — simulation only (uses real type)
module dac_model #(
  parameter      N    = 12,
  parameter real VREF = 3.3
)(
  input  wire [N-1:0] din,    // digital input code
  output real         vout   // analog output (simulation)
);
  // Vout = (D / 2^N) * Vref
  assign vout = ($itor(din) / $itor(1 << N)) * VREF;
endmodule

// R-2R DAC: FPGA drives N output pins into external resistor network
// No special IP — just N GPIO pins + external R/2R resistors
module r2r_dac_driver #(
  parameter N = 8
)(
  input  wire        clk,
  input  wire        rst_n,
  input  wire [N-1:0] code,    // digital value to output
  output reg  [N-1:0] dac_pins  // connect MSB→D7 through external R-2R network
);
  // Register the code to align with external network settling time
  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) dac_pins <= '0;
    else        dac_pins <= code;
  end
endmodule

// Usage note:
// dac_pins[7] (MSB) → 2R shunt to Vout, then R series to dac_pins[6] node
// dac_pins[0] (LSB) → 2R shunt, terminated with 2R to GND
// Vout taken before op-amp buffer for high impedance loads

// PWM-based DAC: digital code → PWM duty → RC filter → analog Vout
// Effective resolution limited by PWM frequency vs ripple tradeoff
module pwm_dac #(
  parameter N = 8      // 8-bit → 256 duty levels
)(
  input  wire        clk,
  input  wire        rst_n,
  input  wire [N-1:0] code,     // 0=0V, 255=Vref (8-bit)
  output wire        pwm_out  // connect to external RC low-pass filter
);
  reg [N-1:0] cnt;

  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) cnt <= '0;
    else        cnt <= cnt + 1;
  end

  assign pwm_out = (cnt < code);
  // External: pwm_out → 10kΩ → Vout → 100nF → GND
  // f_pwm = f_clk/256; filter cutoff ≈ f_pwm/10 for <1% ripple
endmodule

// SPI interface to drive external DAC (e.g. MCP4921 12-bit SPI DAC)
// Sends 16-bit frame: [4 config bits][12 data bits]
module spi_dac_ctrl (
  input  wire        clk,
  input  wire        rst_n,
  input  wire [11:0] dac_code,  // 12-bit DAC value
  input  wire        send,      // pulse to trigger SPI transfer
  output reg         sck,       // SPI clock
  output reg         mosi,      // SPI data
  output reg         cs_n,      // Chip select (active low)
  output reg         done       // Transfer complete
);
  reg [15:0] shift_reg;
  reg [4:0]  bit_cnt;
  reg         busy;

  // MCP4921 frame: 0011 + 12-bit code (BUF=0, GA=1, SHDN=1)
  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      cs_n <= 1; sck <= 0; mosi <= 0; done <= 0; busy <= 0;
    end else if (send && !busy) begin
      shift_reg <= {4'b0011, dac_code};  // load frame
      bit_cnt   <= 15;
      cs_n      <= 0;   // assert CS
      busy      <= 1;
      done      <= 0;
    end else if (busy) begin
      sck  <= ~sck;           // toggle clock
      if (!sck) begin        // output on falling edge
        mosi      <= shift_reg[15];
        shift_reg <= shift_reg << 1;
        if (bit_cnt == 0) begin
          cs_n <= 1; busy <= 0; done <= 1;
        end else bit_cnt <= bit_cnt - 1;
      end
    end else done <= 0;
  end
endmodule