TOPIC 34 — Boolean Minimization

Karnaugh Map Solver

Click cells to enter 0, 1, or X (don't-care). Groups auto-detect, SOP expression simplifies instantly, and Verilog assign is generated for you.

Interactive K-Map Solver
Click a cell to cycle: 01X → 0

01 What is a Karnaugh Map?

A Karnaugh map (K-map) is a visual tool for minimizing Boolean logic expressions. Instead of applying complex algebraic laws, you simply group adjacent 1s on a grid — the grouping rules ensure maximum simplification automatically.

K-maps are essential in digital logic design: they determine the minimum number of gates needed to implement a truth table, directly reducing chip area and power consumption.

WHY GRAY CODE ORDER? (AB: 00 → 01 → 11 → 10) CD=00 CD=01 CD=11 CD=10 AB=00 AB=01 AB=11 AB=10 m0 m1 m3 m2 m4 m5 m7 m6 Key: Adjacent cells differ by 1 bit only → m0(0000) and m1(0001): differ in D only ✓ → m1(0001) and m3(0011): differ in C only ✓ → m3(0011) and m2(0010): differ in D only ✓ This is why groups represent a single literal!

02 K-Map Grouping Rules

Group Size

Groups must have 1, 2, 4, 8, or 16 cells — always a power of 2. Larger groups = simpler expression.

Rectangle Only

Groups must be rectangular (including wrapping). L-shapes, diagonals, and T-shapes are NOT valid.

Wrapping Allowed

Groups can wrap around edges and corners of the map. Corner cells are adjacent to each other diagonally.

Maximize Size

Always find the largest possible group first. Every 1 must be covered. Don't-cares can be included to enlarge groups.

03 Worked Example — 3-Variable K-Map

Truth table: F(A,B,C) = Σm(1,3,5,7) — minterm 1,3,5,7 all equal 1. What is the simplified expression?

RowABCFGroup
00000
10011Group A
20100
30111Group A
41000
51011Group A
61100
71111Group A

All 4 ones are in cells where C=1. One group of 4 → only C survives → F = C

Insight: When 1s appear in all cells where one variable is 1 (regardless of others), that variable alone determines the output. The K-map makes this obvious visually — the entire right column of a 3-var map is C=1.

04 K-Map Result to Verilog

Each group in the SOP K-map becomes one AND term. The terms are ORed together to form the complete expression.

verilog
// K-map result: F = A'B + CD'
// Group 1 (green):  A'B   → cells where A=0, B=1
// Group 2 (blue):   CD'   → cells where C=1, D=0

assign F = (~A & B) | (C & ~D);

// With don't cares: F = Σm(1,3,5,7) + d(2,6)
// Simplified: F = C (single variable after using don't-cares)
assign F_dc = C;

// 4-variable example: F = Σm(0,1,2,3,8,9,10,11)
// K-map gives: F = A'  (top two rows)
assign F_4v = ~A;

FAQ Karnaugh Map Questions

What is a Karnaugh map? +

A Karnaugh map (K-map) is a visual method for simplifying Boolean algebra expressions. It arranges truth table values in a grid where adjacent cells differ by only one variable, making it easy to identify groups of 1s that represent simplified terms. K-maps eliminate the need for complex algebraic manipulation.

How do you group cells in a Karnaugh map? +

Groups must contain 1, 2, 4, 8, or 16 cells (powers of 2). All cells must be 1s (or don't-cares). Groups must be rectangular and can wrap around edges. Always make groups as large as possible to maximize simplification.

What is SOP and POS in K-map? +

SOP (Sum of Products) groups the 1s — each group produces an AND term, all terms ORed. POS (Product of Sums) groups the 0s — each group produces an OR term, all terms ANDed. SOP maps directly to AND-OR logic (NAND-NAND in real gates).

What are don't cares in a Karnaugh map? +

Don't cares (X) are input combinations that either never occur or whose output doesn't matter. You can treat them as 0 or 1 — whichever allows forming larger groups and producing a simpler expression.

How do you convert a K-map result to Verilog? +

Each SOP group becomes an AND term in a Verilog assign. For example, F = AB' + CD becomes: assign F = (A & ~B) | (C & D); The K-map result maps directly to combinational logic.

What is the maximum number of variables a K-map can handle? +

K-maps are practical up to 4 variables (16 cells). For more than 4–5 variables, the Quine-McCluskey algorithm or EDA synthesis tools (like Synopsys DC) are preferred for Boolean minimization.

← Logic Gates Mux & Demux → All Digital Topics