Multiplexer and demultiplexer — from basic 2:1 mux to 8:1 mux, truth tables, Boolean equations, Verilog implementation, FPGA usage, and interactive simulator.
A multiplexer selects one of N data inputs and forwards it to a single output. The select lines determine which input is connected. A 4:1 mux has 4 data inputs, 2 select lines (2² = 4), and 1 output.
| S | D0 | D1 | Y Output |
|---|---|---|---|
| 0 | 0 | X | 0 (= D0) |
| 0 | 1 | X | 1 (= D0) |
| 1 | X | 0 | 0 (= D1) |
| 1 | X | 1 | 1 (= D1) |
Boolean equation: Y = S'·D0 + S·D1
| S1 | S0 | Selected Input | Y |
|---|---|---|---|
| 0 | 0 | D0 | Y = D0 |
| 0 | 1 | D1 | Y = D1 |
| 1 | 0 | D2 | Y = D2 |
| 1 | 1 | D3 | Y = D3 |
module mux2to1 #(parameter W=1) ( input [W-1:0] d0, d1, input sel, output [W-1:0] y ); assign y = sel ? d1 : d0; endmodule
module mux4to1 #(parameter W=8) ( input [W-1:0] d0, d1, d2, d3, input [1:0] sel, output reg [W-1:0] y ); always @(*) begin case (sel) // synthesis parallel_case 2'b00: y = d0; 2'b01: y = d1; 2'b10: y = d2; 2'b11: y = d3; endcase end endmodule
module mux_n #( parameter N = 4, // number of inputs (must be power of 2) parameter W = 8, // data width localparam SEL = $clog2(N) ) ( input logic [W-1:0] d[N], input logic [SEL-1:0] sel, output logic [W-1:0] y ); assign y = d[sel]; // Synthesis infers mux tree endmodule
module mux8to1 ( input [7:0] d, // 8 single-bit inputs input [2:0] sel, output y ); assign y = d[sel]; endmodule
A demultiplexer routes a single input to one of N outputs based on select lines. The unselected outputs are driven to 0.
| S1 | S0 | Y0 | Y1 | Y2 | Y3 |
|---|---|---|---|---|---|
| 0 | 0 | IN | 0 | 0 | 0 |
| 0 | 1 | 0 | IN | 0 | 0 |
| 1 | 0 | 0 | 0 | IN | 0 |
| 1 | 1 | 0 | 0 | 0 | IN |
module demux1to4 #(parameter W=8) ( input [W-1:0] in, input [1:0] sel, output reg [W-1:0] y0, y1, y2, y3 ); always @(*) begin {y0, y1, y2, y3} = '0; // default: all outputs zero case (sel) 2'b00: y0 = in; 2'b01: y1 = in; 2'b10: y2 = in; 2'b11: y3 = in; endcase end endmodule
CPU datapaths use muxes to select between register values, immediate operands, or forwarded results. A RISC-V ALU has muxes on both operand inputs.
In multi-master bus systems, muxes route the winning master's signals onto the shared bus. Combined with an arbiter to generate the select signal.
Any n-variable function can be implemented with a single 2ⁿ:1 mux. Connect truth table values to data inputs, variables to select lines.
Demux routes write data to one of N memory banks based on the address MSBs. Used in banked memory architectures for parallel access.
A 4:1 mux can implement any 2-variable Boolean function. Connect the truth table output values to D0–D3, and input variables A,B to S1,S0:
// Implement F = A XOR B using a 4:1 mux // Truth table: F(0,0)=0, F(0,1)=1, F(1,0)=1, F(1,1)=0 mux4to1 xor_mux ( .d0 (1'b0), // AB=00: F=0 .d1 (1'b1), // AB=01: F=1 .d2 (1'b1), // AB=10: F=1 .d3 (1'b0), // AB=11: F=0 .sel({A, B}), .y (F) );
A multiplexer (mux) selects one of N inputs and routes it to a single output. A demultiplexer (demux) takes one input and routes it to one of N outputs. Mux = many-to-one; Demux = one-to-many. Together they form a complete data routing system.
A 4:1 mux needs 2 select lines because 2² = 4. An 8:1 mux needs 3 (2³=8), a 16:1 mux needs 4. Formula: select lines = log₂(N inputs).
Use a case statement: case(sel) 2'b00: y=d0; 2'b01: y=d1; 2'b10: y=d2; 2'b11: y=d3; endcase or the array index form: assign y = d[sel]; Both synthesize correctly.
Yes. A 2ⁿ:1 mux can implement any n-variable function by connecting truth table values (0/1) to data inputs and variables to select lines. A 4:1 mux covers any 2-variable function; 8:1 covers any 3-variable function.
Muxes are used in: ALU operand selection, bus arbitration, memory bank selection, clock source selection, data compression (time-division multiplexing), FPGA routing matrices, and implementing arbitrary Boolean functions.