A FinFET is a transistor whose channel is raised into a thin vertical fin of silicon, with the gate wrapping around three sides of that fin. Compared with the older flat planar transistor, where the gate only touches the channel from the top, the wrap-around gate gives much stronger electrostatic control, sharply reducing leakage and allowing the transistor to keep shrinking. Intel introduced FinFETs commercially around its 22nm node in 2011-2012, and they were used down to about the 5nm generation.

What is a gate-all-around (GAA) transistor?

A gate-all-around (GAA) transistor, usually built as stacked horizontal nanosheets, has the gate completely surrounding the channel on all four sides. This is the next step after the FinFET's three-sided gate and gives even better control of the channel, lower leakage and tunable drive strength by varying nanosheet width. GAA nanosheet transistors power the leading-edge 3nm and 2nm-class nodes.

Why did transistors move from planar to FinFET to GAA?

As channels shrank, the gate lost control over them - the source and drain fields started to dominate, causing short-channel effects like subthreshold leakage and drain-induced barrier lowering, so the transistor could no longer be turned fully off and wasted power. The fix each time was to give the gate more surface contact with the channel: planar (one side) gave way to FinFET (three sides), which gave way to GAA (all four sides), each restoring electrostatic control at smaller dimensions.

What comes after GAA transistors?

Research directions beyond nanosheet GAA include the CFET (complementary FET), which stacks the n-type and p-type transistors on top of each other to save area, the forksheet which packs nFET and pFET closer, and longer-term ideas using 2D materials or carbon nanotubes as the channel. The general theme remains maximising gate control and density as classical scaling slows.

FinFET vs GAA — How the Modern Transistor Evolved (Planar → FinFET → Nanosheet)

First principles

A transistor is a switch — and the gate is the switch

A MOSFET has three key terminals: a source, a drain, and a gate over the channel between them. Put a voltage on the gate and it creates a conducting channel so current flows source→drain (ON); remove it and the channel vanishes (OFF). A chip is billions of these switches.

The whole game is how well the gate controls that channel. A perfect gate turns the channel fully on and fully off. The story of FinFET and GAA is the story of fighting to keep that control as the transistor shrinks.

The problem

When small transistors stop turning off

In a flat (planar) transistor the gate only touches the channel from the top. That's fine when the channel is long. But as we shrank the channel below ~20–30 nm, the source and drain — which sit right at the channel's ends — got so close that their electric fields started controlling the channel too, fighting the gate. The consequences, called short-channel effects:

Subthreshold leakage — the transistor can't turn fully OFF; current trickles through even when it should be closed.
DIBL (drain-induced barrier lowering) — the drain voltage lowers the barrier the gate is trying to hold up.
Static power waste — billions of leaky "off" transistors burn energy and heat doing nothing.

Below roughly the 22 nm node, the flat gate simply couldn't keep up. The fix was conceptually simple: give the gate more contact with the channel.

💡 Analogy

Imagine pinching a garden hose to stop the water. Press from one side (planar) and a thin hose still leaks. Wrap your hand around three sides (FinFET), or grip it all the way around (GAA), and you shut it off cleanly. More wrap = more control.

The three structures

Planar → FinFET → Gate-All-Around

Each generation gives the gate more surface contact with the channel. Here are the cross-sections (looking down the channel), with the gate wrapping the channel:

Figure 1 — Cross-sections: the gate wraps more of the channel each generation — 1 side (planar) → 3 sides (FinFET) → all 4 (GAA nanosheet).

Generation 1

Planar — the flat original

For decades, transistors were planar: source, drain and channel lying flat, gate sitting on top. Simple to make, and it scaled beautifully through the 1970s–2000s. But with the gate touching only the top of the channel, it ran out of electrostatic control around the 28/22 nm generation — leakage became unmanageable. A new shape was needed.

Generation 2

FinFET — stand the channel up

The breakthrough: instead of a flat channel, etch it into a thin vertical fin of silicon and drape the gate over it so it wraps three sides (top + both flanks). This is a FinFET (Intel branded its version "Tri-Gate"), introduced commercially around 22 nm in 2011–2012.

Three-sided control — the gate now grips the thin fin from three sides, slashing leakage and letting the transistor switch cleanly at low voltage.
Drive strength via fin count — need more current? Use multiple parallel fins.
FinFETs powered everything from ~16/14 nm down to ~5 nm — a remarkable decade-long run.

FinFET is why your phone chips kept improving through the 2010s without melting. (See the timeline in Transistor Size Evolution.)

Generation 3

Gate-All-Around (GAA) — wrap it completely

By the 3 nm era even three-sided control wasn't enough. The answer: lay the channel as horizontal nanosheets and let the gate material flow completely around all four sides of each sheet — Gate-All-Around (GAA), also called nanosheet (or nanowire) FET. Samsung shipped GAA at 3 nm (2022); the 2 nm-class nodes adopt it broadly.

Full wrap = best electrostatics — the gate controls the channel from every side, minimising leakage at the smallest dimensions.
Tunable drive — the nanosheet width can be varied to trade performance vs power, a flexibility FinFET fins didn't offer.
Stacking more sheets adds current without taking more floor area.

GAA is the transistor of the 2 nm generation — the same nodes feeding the AI hardware boom (why chip demand exploded).

Side by side

Planar vs FinFET vs GAA

Structure	Gate wraps	Channel	Era	Why it changed
Planar	1 side (top)	flat	… to ~28/22 nm	lost control → leakage
FinFET	3 sides	vertical fin	~22 nm → ~5 nm	great, but fin control limited at 3 nm
GAA nanosheet	all 4 sides	stacked sheets	~3 nm → 2 nm	best control + tunable width

✅ The one idea behind all of it

Every leap does the same thing: wrap the gate around more of the channel to restore control as the transistor shrinks. 1 side → 3 sides → 4 sides. The transistor changed shape so the gate could keep winning the tug-of-war against leakage.

What's next

Beyond GAA

You can't wrap a gate around more than "all sides," so future gains shift to stacking and new materials:

CFET (Complementary FET) — stack the n-type transistor directly on top of the p-type one to roughly halve the footprint.
Forksheet — pack n and p devices closer with a dielectric wall between them.
2D-material & nanotube channels — atom-thin channels (MoS₂, graphene, carbon nanotubes) for control beyond what silicon allows. (See Transistor Evolution for the long view.)

Reference

FAQ

What is a FinFET?

A transistor whose channel is a thin vertical fin with the gate wrapping three sides — far better control and less leakage than a flat planar device. Used ~22 nm to ~5 nm.

What is GAA / nanosheet?

Gate-all-around: stacked horizontal channel sheets with the gate surrounding all four sides — the best electrostatic control, used at 3 nm and 2 nm.

Why did the shape keep changing?

Shrinking channels suffer short-channel effects (leakage, DIBL). Wrapping the gate around more of the channel restores control — 1 → 3 → 4 sides.

What comes after GAA?

CFET (stacking n over p), forksheet, and eventually 2D-material or nanotube channels.