From a one-line idea to a manufacturable layout. Press play and watch the design transform through every stage of RTL-to-GDSII — then click any stage to dive deep.
Turning a chip idea into silicon is an assembly line of its own. The VLSI design flow (often summarised as RTL-to-GDSII) splits into a front-end (logical) half — define what the chip does — and a back-end (physical) half — turn that logic into a manufacturable layout. Here's each stage in depth.
Everything starts here. The team translates a product idea into a hard specification: the functions, the throughput/latency targets, and the PPA budget — Performance (clock frequency), Power, and Area (cost). They pick the process node (e.g. a 5nm or 28nm library), the key IP and macros to reuse, and define every interface, clock and reset.
Engineers describe the hardware's behaviour in a hardware description language — Verilog or SystemVerilog — at the register-transfer level: registers, combinational logic, datapaths, FSMs and exactly what moves on each clock edge. This is the human-authored "source code" of the chip.
Before spending millions on masks, you must prove the RTL is correct. Verification is the largest single effort on most projects (commonly 60–70%). It builds testbenches — typically SystemVerilog with UVM — driving constrained-random stimulus and directed tests, checking results with scoreboards and assertions (SVA), and measuring functional & code coverage to know when "enough" testing is done.
A synthesis tool converts RTL into a gate-level netlist — real gates and flip-flops chosen from a standard-cell library — optimised against the target technology. You steer it with SDC constraints (clock periods, input/output delays, false/multicycle paths).
Design-for-test makes the manufactured chip testable for fabrication defects. It bridges front-end and back-end and is a guaranteed step on every production chip.
Physical design begins. Floorplanning sets the die and core area and the target utilisation % (how full the core is), positions large macros (SRAMs, IP) and the I/O pads, and plans the power-delivery network (rings and straps).
The tool positions the thousands-to-millions of standard cells into the core's rows, minimising total wirelength and avoiding congestion (too many wires wanting the same region) while respecting timing.
The clock must arrive at every flip-flop at almost the same instant. The spread is clock skew, and CTS builds a balanced distribution network — often an H-tree with carefully sized clock buffers — to keep skew tiny across the whole die.
Now connect everything. Routing lays down metal wires across the stack's many layers to wire up every net — signal, clock and power — with no shorts and no design-rule violations.
The final gate. Multiple signoff checks must all pass:
Pass them all and the layout is exported as a GDSII (or OASIS) file and taped out to the foundry to make masks. Curious which of these stages is a career? See the VLSI Career Roadmap.
| # | Stage | Input | Output | Typical tools |
|---|---|---|---|---|
| 1 | Specification | Idea, requirements | Architecture + PPA spec | C/C++, Python, SystemC |
| 2 | RTL Design | Spec | Synthesizable RTL | Verilog, SystemVerilog |
| 3 | Verification | RTL + spec | Verified RTL, coverage | UVM, simulators, formal |
| 4 | Synthesis | RTL + library + SDC | Gate netlist | DC, Genus, Yosys |
| 5 | DFT | Netlist | Scan-inserted netlist | Tessent |
| 6 | Floorplan | Netlist, die, macros | Floorplan + power grid | Innovus, Fusion, OpenROAD |
| 7 | Placement | Floorplan + netlist | Placed design | Innovus, ICC2 |
| 8 | CTS | Placed design | Clock tree built | Innovus, ICC2 |
| 9 | Routing | Placed + CTS | Routed layout | Innovus, ICC2, OpenROAD |
| 10 | Signoff/GDSII | Routed layout | GDSII → foundry | PrimeTime, Calibre, Quantus |
The animation shows the stages in order, but real projects loop constantly. If timing doesn't close at routing, you go back to placement — or even RTL. Late fixes are done as small ECOs (Engineering Change Orders) to avoid redoing everything. "Timing closure" is the iterative grind of squeezing out the last violations, and it can take weeks. Each loop is expensive, which is exactly why getting the early stages (spec, RTL, floorplan) right matters so much.
The steps that turn a chip idea into a manufacturable layout: spec → RTL → verification → synthesis → DFT → floorplan → placement → CTS → routing → signoff/GDSII.
The journey from a register-transfer-level description (Verilog) to the GDSII layout file the foundry uses to make masks — via synthesis and physical implementation.
Front-end = spec, RTL, verification, synthesis (the logic). Back-end = floorplanning, placement, CTS, routing, signoff (the physical layout).
Related: VLSI Hub · Career Roadmap · FSM Designer · Verilog Spot the Bug