VLSI Chip Design Flow
Every chip you'll ever work on goes through the same sequence of stages — from a napkin spec to silicon you can hold in your hand. This is the pipeline your work feeds into.
Roles in a Chip Design Team
RTL / Design Engineer
Writes synthesizable Verilog/SystemVerilog. Owns micro-architecture, module interfaces, and CDC/reset strategy. Delivers netlist-clean RTL that meets timing, area, and power targets.
Verification Engineer (VE)
Writes UVM testbenches, constrained-random tests, and coverage plans. Owns functional coverage closure and formal verification. Often the largest team in a design org.
PD / Layout Engineer
Takes the synthesized netlist through floorplanning, power grid, place & route, and physical signoff (DRC, LVS, EM/IR). Lives in ICC2 or Innovus all day.
STA Engineer
Runs static timing analysis in PrimeTime or Tempus. Writes SDC constraints, identifies critical paths, and signs off setup, hold, and OCV corners across PVT.
DFT Engineer
Inserts scan chains, JTAG, BIST, and boundary scan for testability. Ensures post-silicon test coverage meets ATE requirements. Works between RTL and physical.
Analog / AMS Engineer
Designs PLLs, ADCs, DACs, LDOs, and I/O pads in custom or semi-custom layout. Works in Spectre/HSPICE, Virtuoso. Interfaces with digital via validated integration rules.
CAD / EDA Engineer
Maintains the tool flows, PDK, scripting infrastructure, and compute farm. The person everyone calls when a tool crashes. Writes Tcl/Python/Perl automation.
FPGA Engineer
Ports/prototypes ASIC RTL on Xilinx/AMD or Intel FPGA boards. Handles board bringup, debug, and pre-silicon software validation. Bridge between design and SW teams.
Linux Command Quick Reference
EDA tools only run on Linux (mostly RHEL/CentOS). Your design lives on a remote compute server. You SSH in and work entirely in the terminal. Bookmark this section.
Navigation & Files
ls -lh # list files with sizes
cd /proj/myblock # change directory
pwd # print current path
find . -name "*.v" # find all Verilog files
grep -rn "always @" src/
cp file.v file_bk.v
mv old.v new.v
rm -rf old_runs/ # careful!
mkdir -p out/logs
du -sh sim_work/ # disk usage
df -h # disk space leftProcesses & Jobs
ps aux | grep vcs # find running sim
top # live process monitor
kill -9 12345 # force kill PID
nohup ./run.sh & # survive logout
jobs # list background jobs
# LSF compute farm (bsub)
bsub -q normal -J my_sim ./sim.sh
bjobs # list your jobs
bkill 98765 # kill LSF job
# SGE / Grid Engine
qsub -N my_job run.sh
qstat # job statusRemote Access & File Transfer
# SSH into design server
ssh user@chipserver01
# Copy file to/from server
scp local.v user@server:/proj/
scp user@server:/proj/out.log .
# Keep session alive (tmux/screen)
tmux new -s mysim
tmux attach -t mysim
# Ctrl+B D to detach safely
# X11 forwarding for gvim/GUI tools
ssh -X user@server
ssh -Y user@server # trusted (faster)Environment Setup
# In ~/.bashrc or ~/.cshrc
export PATH="/tools/synopsys/vcs/bin:$PATH"
export LM_LICENSE_FILE="1700@licserver"
# Source project setup script
source /proj/myblock/setup.sh
# Check tool version
vcs -version
dc_shell -version
# Module system (if used)
module avail
module load synopsys/vcs/2023
module listgvim / vim Cheatsheet
gvim is vim with a GUI window. Same commands, same modes. Most EDA tools spawn it as the default editor. It feels hostile for the first week — then you'll be faster in it than any IDE.
Modes
Navigation
Edit & Delete
Search & Replace
Multi-file & Splits
Useful .vimrc for HDL
" ~/.vimrc — good defaults for Verilog/SV
set nu " line numbers
set ts=2 sw=2 " 2-space indent
set expandtab " spaces not tabs
set autoindent
set hlsearch " highlight matches
set incsearch " live search
set ignorecase smartcase
syntax on
colorscheme desert
" Highlight trailing whitespace
highlight ExtraWhitespace ctermbg=red
match ExtraWhitespace /\s\+$/
" Toggle line numbers with F2
nnoremap <F2> :set nu!<CR>SVN vs Git — Side by Side
Many foundry-connected teams still use SVN because it handles large binary files (GDSII, Liberty, LEF) and enforces centralized access control that PDK licenses require. Modern RTL teams are shifting to Git. You will likely use both.
| Action | SVN Command | Git Equivalent |
|---|---|---|
| Get a working copy | svn checkout svn://server/repo/trunk . | git clone https://server/repo.git |
| Update to latest | svn update | git pull |
| See what changed | svn status | git status |
| See diff | svn diff file.v | git diff file.v |
| Stage a file | (no staging — all tracked files commit) | git add file.v |
| Commit | svn commit -m "fix timing path" | git commit -m "fix timing path" |
| Push to server | (commit IS the push in SVN) | git push origin main |
| Add new file | svn add new_block.v | git add new_block.v |
| View history | svn log -l 20 | git log --oneline -20 |
| Revert a file | svn revert file.v | git checkout -- file.v |
| Create branch | svn copy trunk branches/my_branch | git checkout -b my_branch |
| Blame / annotate | svn blame file.v | git blame file.v |
| Ignore files | svn propset svn:ignore "*.log" . | .gitignore file |
| Resolve conflict | svn resolve --accept mine-full file.v | git mergetool or edit then git add |
EDA Tools You Will Encounter
Three vendors dominate: Synopsys, Cadence, and Siemens EDA (formerly Mentor). Your company will have licenses for some subset. Here's what each tool does.
The largest EDA vendor. Their tools dominate synthesis and STA.
- VCS — industry standard Verilog/SV/UVM simulator
- Design Compiler (DC) — RTL-to-gate synthesis
- IC Compiler 2 (ICC2) — place & route
- PrimeTime (PT) — gold standard STA sign-off
- JasperGold — formal verification (SVA properties)
- Verdi — debug waveform viewer (like DVE but better)
- Formality — formal equivalence checking (RTL vs netlist)
- StarRC — parasitic extraction
Strong in custom/analog (Virtuoso) and increasingly in digital flow.
- Xcelium — Verilog/SV/UVM simulator (replaces IES/NCSim)
- Genus — RTL synthesis (competitor to DC)
- Innovus — place & route (competitor to ICC2)
- Tempus — STA sign-off tool
- Virtuoso — custom/analog IC layout and schematic
- Spectre — SPICE-level circuit simulation
- Conformal — logic equivalence checking
- Joules — RTL power analysis
Strong in DFT, emulation, and physical verification.
- Questasim / ModelSim — simulator popular in academia & FPGA
- Calibre — gold standard DRC / LVS physical verification
- Questa Formal — formal verification
- Tessent — DFT insertion (scan, BIST, JTAG)
- Veloce — hardware emulation platform
EDA tools are scripted — you'll write automation scripts constantly.
- Tcl — the #1 scripting language in EDA. DC, PT, ICC2, Innovus all use Tcl for command-line and batch scripting
- Python — increasingly used for regression scripts, coverage analysis, and test infrastructure
- Perl — legacy parsing scripts everywhere. Still alive in old flows
- Make / Makefile — runs the flow; targets like
sim,synth,sta - Shell (bash/csh) — job submission, environment setup
Basic Tcl You Need to Know
# Tcl basics — used in DC, PrimeTime, ICC2, etc.
# Variables
set top_module "my_chip"
set clk_period 2.0
# If / else
if {$clk_period < 2.0} {
puts "Fast design"
} else {
puts "Standard design"
}
# Loop over a list
foreach module {alu ctrl mem_ctrl} {
analyze -format sverilog src/${module}.sv
}
# String operations
set name [string toupper $top_module]
set path "${top_module}/reports"
file mkdir $path
# In DC: read RTL, synthesize, write netlist
analyze -format sverilog [glob src/*.sv]
elaborate $top_module
create_clock -period $clk_period [get_ports clk]
compile_ultra
write_file -f verilog -out out/netlist.v $top_moduleProtocols Every Intern Should Know
I²C (Inter-Integrated Circuit)
Two wires: SDA (data) and SCL (clock). Open-drain — multiple devices share the bus without contention. Master generates clock and initiates transfers. Each device has a 7-bit (or 10-bit) address. Transfers start with START condition (SDA falls while SCL high), then address+R/W bit, ACK from slave, then data bytes with ACKs, then STOP.
SPI (Serial Peripheral Interface)
Four wires: SCLK, MOSI (master out), MISO (master in), CS̄ (chip select, active low). Full duplex — data flows both directions simultaneously. No ACK — master must know transfer length. CPOL (clock polarity) and CPHA (clock phase) define 4 modes. Mode 0 (CPOL=0, CPHA=0) is most common.
UART (Universal Async Rx/Tx)
No clock wire — both sides agree on baud rate. Frame: 1 start bit (LOW), 8 data bits (LSB first), optional parity bit, 1-2 stop bits (HIGH). Common baud rates: 9600, 115200. Still used heavily for debug consoles on SoCs. TX of one device connects directly to RX of the other.
AXI4 (Advanced eXtensible Interface)
ARM's AMBA AXI4 is the dominant SoC interconnect. Five independent channels: AW (write address), W (write data), B (write response), AR (read address), R (read data). Handshake: valid+ready on every channel. Supports burst transfers (up to 256 beats), out-of-order transactions via ID tags, and separate read/write paths for maximum throughput.
APB (Advanced Peripheral Bus)
Simple, low-power peripheral bus. Single address+data phase — no pipelining, no burst. Used for config registers (UART, GPIO, timers) that don't need high bandwidth. Signals: PSEL, PENABLE, PWRITE, PADDR, PWDATA, PRDATA, PREADY. Two-phase: Setup (PSEL+PWRITE+PADDR asserted) → Access (PENABLE asserted, wait for PREADY).
PCIe (Peripheral Component Interconnect Express)
High-speed serial with differential pairs. Each lane is a pair of TX and RX pairs (4 wires per lane). Links: x1, x4, x8, x16. Uses TLP (Transaction Layer Packets) for read/write requests. Gen 4: 16 GT/s per lane = ~2GB/s. Requires clock recovery (CDR), 128b/130b encoding, and flow control credits. Dominant for GPU-to-CPU and NVMe SSD interfaces.
Acronym Glossary — Search Instantly
Semiconductor conversations are 40% acronyms. Use the search box — start typing any letter.
Frequently Asked Questions
What is the VLSI design flow?
Spec → RTL Design (Verilog/SV) → Functional Verification (UVM simulation) → Logic Synthesis (RTL to gate netlist) → Place & Route → Signoff (STA, DRC, LVS) → Tapeout (GDSII to foundry) → Fabrication → Package & Test. Each stage has EDA tools and formal sign-off criteria before proceeding.
Why does everyone use gvim instead of VS Code?
Your RTL lives on a remote compute server (Linux). You SSH in over a corporate network. gvim runs perfectly over SSH+X11 with zero latency on the server side. VS Code remote-SSH works but requires network stability. More importantly, EDA tools (DC, PT) will open files in your $EDITOR which defaults to vi/gvim. Learn it once, use it forever.
Why do companies still use SVN?
SVN handles large binary files (GDSII = GBs, Liberty = hundreds of MB), enforces per-directory access control compatible with PDK NDA licensing, and has 20+ years of EDA tool integration. Also: most engineers who set up the flow 10 years ago knew SVN. Git is winning for RTL code at modern companies but SVN still dominates full project repos.
What protocol should I understand first — AXI or APB?
Learn AXI4-Lite first — it's the simplified version (no bursts, no out-of-order) used for configuration registers. You'll write/read registers on virtually every SoC block. Then learn full AXI4 for DMA and memory-mapped peripherals. APB is even simpler and worth knowing for very lightweight peripherals. AXI handshake (valid+ready) is the single most important concept.
What is Tapeout?
Tapeout is when the final chip design (GDSII layout file) is sent to the foundry (e.g., TSMC) for manufacturing. The name comes from when designs were literally sent on magnetic tape. After tapeout, you wait 8–16 weeks for silicon to come back. It's the biggest milestone in a chip project — celebrated with champagne, then followed immediately by anxiety about silicon bring-up.