HBM3 AXI4 Host Interface

// hbm3_axi4_if.v — AXI4 Slave Interface for HBM3 Controller
// Phase 3 Module 12 · EcrioniX — https://ecrionix.org/hbm3-controller/axi4-if/

module hbm3_axi4_if #(
    parameter MAX_ID = 8   // outstanding write IDs
) (
    // AXI4 global
    input  wire         i_aclk,
    input  wire         i_aresetn,

    // AW channel (master → slave)
    input  wire [7:0]   i_awid,
    input  wire [33:0]  i_awaddr,
    input  wire [7:0]   i_awlen,
    input  wire         i_awvalid,
    output reg          o_awready,

    // W channel
    input  wire [255:0] i_wdata,
    input  wire [31:0]  i_wstrb,
    input  wire         i_wlast,
    input  wire         i_wvalid,
    output reg          o_wready,

    // B channel
    output reg  [7:0]   o_bid,
    output reg  [1:0]   o_bresp,
    output reg          o_bvalid,
    input  wire         i_bready,

    // AR channel
    input  wire [7:0]   i_arid,
    input  wire [33:0]  i_araddr,
    input  wire [7:0]   i_arlen,
    input  wire         i_arvalid,
    output reg          o_arready,

    // R channel
    output reg  [7:0]   o_rid,
    output reg  [255:0] o_rdata,
    output reg  [1:0]   o_rresp,
    output reg          o_rlast,
    output reg          o_rvalid,
    input  wire         i_rready,

    // To HBM3 engine
    output reg          o_req_valid,
    output reg          o_req_wr,
    output reg  [33:0]  o_req_addr,
    output reg  [255:0] o_req_data,
    output reg  [31:0]  o_req_mask,
    input  wire         i_req_ready,

    // From HBM3 engine
    input  wire [255:0] i_rd_data,
    input  wire         i_rd_valid,
    input  wire         i_wr_done
);

// ── RESP constants ──────────────────────────────────
localparam [1:0]
    RESP_OKAY   = 2'b00,
    RESP_SLVERR = 2'b10;

// ── Write FSM ───────────────────────────────────────
localparam [2:0]
    WS_IDLE   = 3'b000,
    WS_AW     = 3'b001,  // waiting for AW (W already arrived)
    WS_W      = 3'b010,  // waiting for W  (AW already arrived)
    WS_REQ    = 3'b011,  // issuing HBM3 write request
    WS_WAIT   = 3'b100,  // waiting for i_wr_done
    WS_BRESP  = 3'b101;  // B channel handshake

reg [2:0]   wr_state;
reg [7:0]   r_awid;
reg [33:0]  r_awaddr;
reg [255:0] r_wdata;
reg [31:0]  r_wstrb;
reg          r_aw_got, r_w_got;

always @(posedge i_aclk or negedge i_aresetn) begin
    if (!i_aresetn) begin
        wr_state   <= WS_IDLE;
        o_awready  <= 1'b1;
        o_wready   <= 1'b1;
        o_bvalid   <= 1'b0;
        o_bid      <= 8'h0;
        o_bresp    <= RESP_OKAY;
        o_req_valid <= 1'b0;
        o_req_wr   <= 1'b0;
        o_req_addr <= 34'h0;
        o_req_data <= 256'h0;
        o_req_mask <= 32'h0;
        r_aw_got   <= 1'b0;
        r_w_got    <= 1'b0;
    end else begin

        // Accept AW when idle or waiting-for-AW
        if (i_awvalid && o_awready) begin
            r_awid   <= i_awid;
            r_awaddr <= i_awaddr;
            r_aw_got <= 1'b1;
            o_awready <= 1'b0;  // close until current txn done
        end

        // Accept W when idle or waiting-for-W
        if (i_wvalid && o_wready) begin
            r_wdata  <= i_wdata;
            r_wstrb  <= i_wstrb;
            r_w_got  <= 1'b1;
            o_wready  <= 1'b0;
        end

        case (wr_state)
            WS_IDLE: begin
                if (r_aw_got && r_w_got)
                    wr_state <= WS_REQ;
            end

            WS_REQ: begin
                o_req_valid <= 1'b1;
                o_req_wr    <= 1'b1;
                o_req_addr  <= r_awaddr;
                o_req_data  <= r_wdata;
                o_req_mask  <= r_wstrb;
                if (i_req_ready) begin
                    o_req_valid <= 1'b0;
                    wr_state    <= WS_WAIT;
                end
            end

            WS_WAIT: begin
                if (i_wr_done) begin
                    o_bvalid <= 1'b1;
                    o_bid    <= r_awid;
                    o_bresp  <= RESP_OKAY;
                    wr_state <= WS_BRESP;
                end
            end

            WS_BRESP: begin
                if (i_bready) begin
                    o_bvalid  <= 1'b0;
                    r_aw_got  <= 1'b0;
                    r_w_got   <= 1'b0;
                    o_awready <= 1'b1;
                    o_wready  <= 1'b1;
                    wr_state  <= WS_IDLE;
                end
            end

            default: wr_state <= WS_IDLE;
        endcase
    end
end

// ── Read FSM ────────────────────────────────────────
localparam [1:0]
    RS_IDLE  = 2'b00,
    RS_REQ   = 2'b01,  // issuing HBM3 read request
    RS_WAIT  = 2'b10,  // waiting for i_rd_valid
    RS_RRESP = 2'b11;  // R channel handshake

reg [1:0]   rd_state;
reg [7:0]   r_arid;
reg [33:0]  r_araddr;

always @(posedge i_aclk or negedge i_aresetn) begin
    if (!i_aresetn) begin
        rd_state   <= RS_IDLE;
        o_arready  <= 1'b1;
        o_rvalid   <= 1'b0;
        o_rlast    <= 1'b0;
        o_rid      <= 8'h0;
        o_rdata    <= 256'h0;
        o_rresp    <= RESP_OKAY;
    end else begin
        case (rd_state)
            RS_IDLE: begin
                if (i_arvalid && o_arready) begin
                    r_arid    <= i_arid;
                    r_araddr  <= i_araddr;
                    o_arready <= 1'b0;
                    rd_state  <= RS_REQ;
                end
            end

            RS_REQ: begin
                o_req_valid <= 1'b1;
                o_req_wr    <= 1'b0;
                o_req_addr  <= r_araddr;
                o_req_data  <= 256'h0;
                o_req_mask  <= 32'hFFFF_FFFF;
                if (i_req_ready) begin
                    o_req_valid <= 1'b0;
                    rd_state    <= RS_WAIT;
                end
            end

            RS_WAIT: begin
                if (i_rd_valid) begin
                    o_rdata  <= i_rd_data;
                    o_rid    <= r_arid;
                    o_rresp  <= RESP_OKAY;
                    o_rlast  <= 1'b1;
                    o_rvalid <= 1'b1;
                    rd_state <= RS_RRESP;
                end
            end

            RS_RRESP: begin
                if (i_rready) begin
                    o_rvalid  <= 1'b0;
                    o_rlast   <= 1'b0;
                    o_arready <= 1'b1;
                    rd_state  <= RS_IDLE;
                end
            end

            default: rd_state <= RS_IDLE;
        endcase
    end
end

endmodule

// tb_hbm3_axi4_if.sv — AXI4 interface testbench
`timescale 1ns/1ps

module tb_hbm3_axi4_if;

// ── DUT signals ─────────────────────────────────────
logic         i_aclk, i_aresetn;
logic [7:0]   i_awid;
logic [33:0]  i_awaddr;
logic [7:0]   i_awlen;
logic         i_awvalid;
logic         o_awready;
logic [255:0] i_wdata;
logic [31:0]  i_wstrb;
logic         i_wlast, i_wvalid;
logic         o_wready;
logic [7:0]   o_bid;
logic [1:0]   o_bresp;
logic         o_bvalid;
logic         i_bready;
logic [7:0]   i_arid;
logic [33:0]  i_araddr;
logic [7:0]   i_arlen;
logic         i_arvalid;
logic         o_arready;
logic [7:0]   o_rid;
logic [255:0] o_rdata;
logic [1:0]   o_rresp;
logic         o_rlast, o_rvalid;
logic         i_rready;
// HBM3 engine side
logic         o_req_valid, o_req_wr;
logic [33:0]  o_req_addr;
logic [255:0] o_req_data;
logic [31:0]  o_req_mask;
logic         i_req_ready;
logic [255:0] i_rd_data;
logic         i_rd_valid, i_wr_done;

hbm3_axi4_if dut (.*);

// ── Clock 500 MHz ────────────────────────────────────
initial i_aclk = 0;
always #1 i_aclk = ~i_aclk;

// ── SVA: BVALID must deassert after BREADY ───────────
assert property (@(posedge i_aclk) disable iff (!i_aresetn)
    (o_bvalid && i_bready) |=> !o_bvalid)
else $error("BVALID not deasserted after BREADY at %0t", $time);

// ── SVA: RVALID must deassert after RREADY ───────────
assert property (@(posedge i_aclk) disable iff (!i_aresetn)
    (o_rvalid && i_rready) |=> !o_rvalid)
else $error("RVALID not deasserted after RREADY at %0t", $time);

// ── SVA: AWREADY stable until handshake ──────────────
assert property (@(posedge i_aclk) disable iff (!i_aresetn)
    (i_awvalid && !o_awready) |=> i_awvalid)
else $error("Master dropped AWVALID before handshake at %0t", $time);

// ── HBM3 model: accept request after 1 cycle ─────────
initial i_req_ready = 0;
always @(posedge i_aclk) begin
    i_req_ready <= o_req_valid;  // 1-cycle latency accept
end

// ── HBM3 model: return write done / read data ────────
always @(posedge i_aclk) begin
    i_wr_done  <= 1'b0;
    i_rd_valid <= 1'b0;
    i_rd_data  <= 256'h0;
    if (i_req_ready && o_req_valid) begin
        if (o_req_wr) begin
            repeat(3) @(posedge i_aclk);
            i_wr_done <= 1'b1;
        end else begin
            repeat(5) @(posedge i_aclk);
            i_rd_data  <= 256'hDEADBEEF_CAFEBABE_12345678_ABCDEF01_
                           FEEDFACE_BAADF00D_DEADC0DE_0BADF00D;
            i_rd_valid <= 1'b1;
        end
    end
end

task automatic axi4_write(
    input [7:0]   id,
    input [33:0]  addr,
    input [255:0] data
);
    // AW channel
    @(posedge i_aclk);
    i_awid    = id;
    i_awaddr  = addr;
    i_awlen   = 8'h00;
    i_awvalid = 1'b1;
    // W channel (same cycle)
    i_wdata   = data;
    i_wstrb   = 32'hFFFF_FFFF;
    i_wlast   = 1'b1;
    i_wvalid  = 1'b1;
    @(posedge i_aclk iff (o_awready && o_wready));
    i_awvalid = 1'b0;
    i_wvalid  = 1'b0;
    // B channel
    i_bready  = 1'b1;
    @(posedge i_aclk iff o_bvalid);
    $display("[%0t] WRITE DONE id=%0h addr=%0h bresp=%0b",
             $time, o_bid, addr, o_bresp);
    @(posedge i_aclk);
    i_bready  = 1'b0;
endtask

task automatic axi4_read(
    input [7:0]  id,
    input [33:0] addr
);
    @(posedge i_aclk);
    i_arid    = id;
    i_araddr  = addr;
    i_arlen   = 8'h00;
    i_arvalid = 1'b1;
    @(posedge i_aclk iff o_arready);
    i_arvalid = 1'b0;
    i_rready  = 1'b1;
    @(posedge i_aclk iff o_rvalid);
    $display("[%0t] READ DONE id=%0h data=%0h rresp=%0b",
             $time, o_rid, o_rdata, o_rresp);
    @(posedge i_aclk);
    i_rready  = 1'b0;
endtask

initial begin
    {i_awvalid,i_wvalid,i_arvalid,i_bready,i_rready} = 5'h0;
    i_aresetn = 0;
    repeat(4) @(posedge i_aclk);
    i_aresetn = 1;
    repeat(2) @(posedge i_aclk);

    $display("=== TEST 1: AXI4 Write ===");
    axi4_write(8'h05, 34'h1000, 256'hA5A5A5A5);

    repeat(2) @(posedge i_aclk);

    $display("=== TEST 2: AXI4 Read ===");
    axi4_read(8'h07, 34'h1000);

    repeat(2) @(posedge i_aclk);

    $display("=== TEST 3: Back-to-back Write then Read ===");
    axi4_write(8'h01, 34'h2000, 256'hDEADBEEF);
    axi4_read (8'h02, 34'h2000);

    repeat(4) @(posedge i_aclk);
    $display("=== ALL AXI4 TESTS PASSED ===");
    $finish;
end
endmodule