All Courses &
Your Learning Roadmap

Learn digital logic, Verilog, simulation, and FPGA implementation from zero. Blink LEDs, build a UART, implement a soft-core processor. No experience required.

Build a RISC-V CPU from scratch — registers, instruction fetch, decode, execute, memory, pipeline stages, hazard detection, branch prediction, and more.

Complete ARM Cortex-M and Cortex-A deep-dive. Instruction set, pipeline, memory model, AMBA/AXI bus, exception handling, cache, TrustZone, and real interview prep.

Build a neural network accelerator on FPGA. CNN inference, INT8 quantisation, systolic array on FPGA, HLS comparison, Vitis AI, roofline model, edge AI deployment.

Walk the full ASIC flow — RTL design, synthesis, static timing analysis, formal verification, DFT insertion, backend handoff, tapeout, and first silicon bring-up.

RTL to GDSII — floorplan, placement, CTS, routing, signoff. IR drop, EM, DRC/LVS, timing closure at advanced nodes. Industry tools: Innovus, ICC2, Calibre, PrimeTime.

Design a complete AI accelerator integrated with RISC-V. Systolic array RTL, RoCC/AXI4 integration, DMA, software driver, INT8 inference, full SoC, FPGA, physical design — 153× speedup over CPU.

Design for Testability from first principles. Fault models, scan design, ATPG, BIST, MBIST, JTAG, boundary scan, fault coverage, DPPM — everything for a DFT engineer role.

Black's equation calculator for electromigration signoff. Input current density and temperature, get wire lifetime and fix suggestions. Used by physical design engineers.

3-tier supply chain analysis of AI hardware companies. Which stocks benefit from growing AI demand — from NVDA and TSM to HBM, EDA, and data centre infrastructure.