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⚡ Live Build · Soft IP Series

Build HBM3 Controller
with Claude

A complete, production-quality High Bandwidth Memory 3 controller built from scratch in Verilog — with AI collaboration, full documentation, and a SystemVerilog testbench for every module.

📋 View Full Roadmap 🚀 Start Phase 1
18
Modules
5
Phases
819
GB/s Bandwidth
16
Pseudo-Channels
100%
Free & Open
Standard: JEDEC JESD238 (HBM3)
Speed: 8 Gbps/pin (HBM3) · 9.6 Gbps (HBM3E)
Width: 1024-bit per stack
Channels: 8 channels × 2 pseudo-channels = 16 PC
Banks: 32 banks per pseudo-channel (8BG × 4B)
Host IF: AXI4 (synthesizable)
PHY: Behavioral model (standard practice)
ECC: SECDED per pseudo-channel
Architecture
HBM3 Controller — Block Diagram
Full stack from AXI4 host interface down to the HBM3 DRAM stack. PHY is a behavioral model; all other blocks are synthesizable Verilog.
AXI4 Host Interface AW / W / B / AR / R channels Request Scheduler & Reorder Buffer priority · bank interleaving · QoS · open/closed page policy Address Mapper Row / Col / BG / Bank / PC / Stack decode Pseudo-Channel Controller × 16 (PC0 – PC15) per-PC: Bank/BG FSM · Row Activation · tRCD/tRAS/tRP/tCL/tWL state machine · page tracking DRAM Timing FSM tRCD·tRAS·tRP·tCL tWL·tRFC·tREFI Bank & BG FSM 8 BG × 4 Banks open / closed state Refresh Controller ABR · PBR (per-bank) tREFI · tRFC Temp Monitor TUF flag · throttle TEMPCO · derate Power Management self-refresh · power-down entry / exit FSM Write Data Path write buffer · DQ/DQS burst align write leveling model · BL8/BL16 ECC Engine (SECDED) single-bit correct · double-bit detect syndrome generation · correction logic Read Data Path read FIFO · DQS capture model CL/CWL latency · data alignment CA Bus Controller Command/Address encoding · parity · pseudo-channel select · CA training model PHY Interface Model (behavioral — not synthesizable) SerDes model · DLL/PLL model · per-pin training · DQ/DQS/CA micro-bump abstraction HBM3 DRAM Stack 8 DRAM dies stacked · 2.5D interposer · micro-bumps · 8 Gbps/pin Synthesizable RTL Behavioral model
Why HBM3?
The Memory at the Heart of Every AI Chip
H100, MI300X, Gaudi3, TPU v5 — they all run on HBM. Understanding its controller is foundational to AI hardware design.
🤖
AI Training & Inference
NVIDIA H100 has 6 HBM3 stacks = 80GB, 3.35 TB/s. AMD MI300X has 8 stacks = 192GB. The memory controller is the bottleneck to GPU performance.
⚡
819 GB/s Per Stack
HBM3 at 8 Gbps/pin × 1024 bits = 819 GB/s. Compare to DDR5 at ~89 GB/s per channel. That's 9× more bandwidth on a single stack.
🔬
No Free RTL Exists
There is no open-source, fully documented HBM3 controller in Verilog anywhere. This build puts EcrioniX in completely uncharted territory.
📐
Chiplet Architecture
HBM sits on a silicon interposer alongside the compute die. Understanding HBM controllers is essential for UCIe and advanced packaging roles.
🏦
Industry Job Demand
Memory controller design roles at NVIDIA, AMD, Micron, SK Hynix, Samsung command $180–280K TC. Almost no engineers specialise in this.
🎓
Deep Learning Opportunity
Building this controller teaches DRAM timing, schedulers, ECC, AXI4, PHY abstraction, and power management — all in one project.
Full Roadmap
5 Phases · 18 Modules · Built Live
Each module = dedicated page with Verilog source, port table, waveform diagram, SystemVerilog testbench, and FAQ. Built one at a time with full documentation.
P2
Phase 2 — Data Path
Write path · Read path · ECC · Address decode · How data actually flows through the controller
✅ Complete
✍️
Module 5 — Write Data Path
Write buffer, CWL pipeline, BL4 burst serializer, DM/DBI handling, DQS enable.
✅ Done
📖
Module 6 — Read Data Path
CL pipeline, DQS capture, burst deserializer, read FIFO, latency error detection.
✅ Done
🛡️
Module 7 — ECC Engine (SECDED)
32-bit data + 7 parity bits. Syndrome generation, single-bit correction, double-bit detection.
✅ Done
🗺️
Module 8 — Address Mapper
34-bit AXI4 address → stack / PC / BG / bank / row / column. Configurable interleave modes.
✅ Done
P3
Phase 3 — Intelligence
Scheduler · Pseudo-channel arbiter · CA bus · Where performance is won or lost
✅ Complete
🧠
Module 9 — Request Scheduler
FR-FCFS algorithm, read/write queues, write-drain watermarks, refresh arbitration.
✅ Done
🔀
Module 10 — Pseudo-Channel Controller
Integration hub for one PC: instantiates Modules 1–4 + 9 with command sequencing FSM.
✅ Done
📡
Module 11 — CA Bus Controller
8-bit CA packet encoding, ACT 2-packet format, CA parity, CKE control, all 7 command types.
✅ Done
🔌
Module 12 — AXI4 Host Interface
Full AXI4 slave: AW/W/B/AR/R channels, ID tracking, 8 outstanding transactions, 256-bit data.
✅ Done
P4
Phase 4 — PHY, Power & Temperature
PHY behavioral model · Power management · Thermal throttling · Bringing it all together
✅ Complete
🔌
Module 13 — PHY Interface Behavioral Model
Behavioral DQ/DQS timing model, PHY init sequence, write leveling, read DQS centering, ZQ cal.
✅ Done
🌡️
Module 14 — Temperature Monitor & Throttle
MR4 temp readback, 3-level throttle FSM, tREFI derating at high temp, emergency shutdown.
✅ Done
💤
Module 15 — Power Management
Self-refresh entry/exit FSM, APD/PPD/SR/DPD modes, CKE control, idle detection, wake latency.
✅ Done
P5
Phase 5 — Verification & Integration
Full SV testbench · HBM3 DRAM behavioral model · Assertions · Coverage · Simulate the whole thing
✅ Complete
🧪
Module 16 — HBM3 DRAM Memory Model
Behavioral DRAM: CA decoder, 32-bank FSM, associative memory array, timing violation checks.
✅ Done
✅
Module 17 — SV Testbench & Verification
AXI4 BFM, scoreboard, functional coverage, 10 test scenarios, SVA assertions, bandwidth benchmark.
✅ Done
📊
Module 18 — Integration & Benchmarks
Top-level instantiation, 819 GB/s benchmark, synthesis results, design decisions, series complete.
✅ Done — Series Complete
Tech Stack
What We're Building With
⚙️
Verilog (RTL)
Synthesizable RTL for all controller modules. Parametrised, clean, Quartus/Vivado compatible.
🧪
SystemVerilog (TB)
Self-checking testbenches, SVA assertions, constrained random stimulus, functional coverage.
🤖
Claude (AI Pair)
Every module co-developed with Claude — RTL, testbench, documentation, and review.
📐
JEDEC JESD238
HBM3 standard specification. All timing parameters, command encoding, and CA protocol from spec.
🔁
AXI4 Protocol
Industry-standard host interface. Compatible with any AXI4 master (ARM Cortex, RISC-V SoC).
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Questa / VCS / Icarus
All testbenches validated with open Icarus Verilog. Also tested on Questa and Synopsys VCS.
JEDEC Spec Reference
HBM3 Key Timing Parameters
All values from JEDEC JESD238. These drive the timing FSM in Module 1.
Parameter Symbol Min What It Controls
RAS to CAS DelaytRCD14 nsTime from ACT to first RD/WR
Row Active TimetRAS32 nsMinimum time row stays open
Precharge TimetRP14 nsPRE to next ACT on same bank
CAS Read LatencyCL35 nsRD command to first data bit
CAS Write LatencyCWL18 nsWR command to first data
Refresh IntervaltREFI3.9 µsMax time between refresh commands
Refresh Cycle TimetRFC220 nsDuration of a refresh operation
Row Cycle TimetRC46 nsACT to ACT on same bank (tRAS+tRP)
Phase 1 starts now — DRAM Timing FSM
The timing FSM is the heartbeat of every DRAM controller. Module 1 covers all JEDEC timing parameters in synthesizable Verilog with a complete SV testbench.
🚀 Start Module 1 — Timing FSM 📚 All Courses
FAQ
Common Questions
Do I need prior DRAM knowledge to follow this?

No. Each module starts from fundamentals. Module 1 explains what tRCD, tRAS, tRP mean physically before writing a single line of Verilog. If you know basic digital design (FSMs, flip-flops, synchronous logic) you can follow along.

Can this RTL actually be taped out or used in FPGA?

The controller RTL (Modules 1–15, excluding the PHY behavioral model) is fully synthesizable. It can be used with a real HBM3 PHY hardmacro from the foundry. On FPGA you'd pair it with an HBM3 soft PHY available on UltraScale+ HBM devices (Xilinx provides the PHY hardblock).

Why not DDR5 instead of HBM3?

DDR5 controllers are well-documented and several open-source implementations exist. HBM3 has no good free RTL reference, the industry demand is exploding (every AI chip uses it), and the pseudo-channel architecture makes it architecturally richer to build and understand.

How long will the full build take?

We're building it live — one module at a time. Phase 1 (4 modules) is the starting point. Each module is a self-contained page with full RTL + testbench. Follow along, bookmark, and build your own version alongside us.