2-Input AND Gate

Verilog problems / Verilog Language Basics

What you must build

Build a 2-input AND gate. Output is 1 only when both inputs are 1.

Engineers use “2-Input AND Gate” as a building block in verilog language basics. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is an introductory kata. Prefer a clear continuous assignment or a small combinational always block. Name the module top_module and keep the port list identical to the table — the hidden testbench instantiates that name.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  a,
  input  b,
  output out
);

  // Your code here

endmodule

Why this shows up in interviews

2-Input AND Gate sits under Verilog Language Basics (combinational, gates). Concept: Use assign out = a & b; or an equivalent continuous assignment.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• Wire the Input Straight to the Output — Connect a single input to a single output with a continuous assignment.

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