Credit-Based Flow Control Counter

Verilog problems / Sequential Design

What you must build

Track available send credits so a sender never transmits more than the receiver has buffer space for — the flow-control mechanism behind NoC and high-speed serial links.

Engineers use “Credit-Based Flow Control Counter” as a building block in sequential design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a medium kata: you will need sequential logic or a small FSM. Decide what is registered versus combinational before you type. Reset polarity and clock edge must match the spec; the judge will fail you on the first mismatched cycle.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  rst,
  input  send,
  input  credit_return,
  output reg [2:0] credits,
  output can_send
);

  // Your code here — MAX=4. can_send=credits!=0. send only decrements when can_send; credit_return
  // increments (capped at MAX). Handle both happening the same cycle without under/overflow.

Why this shows up in interviews

Credit-Based Flow Control Counter sits under Sequential Design (sequential, counter, protocol). Concept: A sender may only spend a credit when it actually has one: if(send && can_send) credits<=credits-1 , alongside independently gaining one back on credit_return . Dropping the can_send guard on the decrement lets send fire with zero credits available, underflowing the counter to its maximum value — which is doubly dangerous here, because can_send is derived from credits!=0 , so the underflow doesn't just corrupt the count, it flips the flow-control gate back to "go ahead and send more" at exactly the moment the sender should be blocked.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• D Flip-Flop with Asynchronous Reset — Standard D flip-flop with an active-low asynchronous reset. Reset clears q immediately, without waiting for a clock edge.
• 4-Bit Shift Register (SIPO) — Serial-in, parallel-out shift register. Each clock, shift left and load sin into the LSB. Sync active-high reset clears q.
• JK Flip-Flop — The flip-flop with no forbidden state: j=k=1 toggles instead of racing. Classic building block for counters.
• 4-Bit Up/Down Counter — A synchronous counter that increments or decrements each clock edge depending on a direction input, with a synchronous reset.

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