RTL Problems / Level 4 · Clock Domain Crossing (CDC)
What You Will Learn
By solving Pulse Synchronizer — Clock-Domain Crossing, you will acquire core industry skills:
- Synthesizable hardware modeling in standard Verilog-2001 / SystemVerilog.
- Correct handling of interface port contracts, edge-triggered clocks, and active-low/high resets.
- Simulation waveform interpretation and debugging using timing diagrams (VCD traces).
- Architectural avoidance of timing violations, glitching hazards, and synthesis warnings.
Problem Statement & Requirements
Design a Toggle-based Pulse Synchronizer to transfer a single-cycle pulse from a fast clock domain (clk_src) to a slow destination domain (clk_dst).
Hardware design teams at leading semiconductor firms evaluate these exact port contracts, race-condition assertions, and corner cases during technical design reviews and ASIC engineer interviews.
Prerequisites: Two-flop synchronizers, toggle flip-flops, rising/falling edge detection.
Port List & Interface Timing
The hidden testbench instantiates top_module. Module port names and bit-widths must match the interface contract exactly:
| Name | Dir | Width | Description |
|---|---|---|---|
clk_src | input | 1 | Source clock domain (fast) |
areset_src_n | input | 1 | Source domain reset |
pulse_src | input | 1 | Single-cycle pulse in source domain |
clk_dst | input | 1 | Destination clock domain (slow) |
areset_dst_n | input | 1 | Destination domain reset |
pulse_dst | output | 1 | Single-cycle pulse in destination domain |
Timing Constraints & Synthesizable RTL Rules
Timing Contract: Input `pulse_src` is a single-cycle strobe in `clk_src`. Output `pulse_dst` asserts for exactly 1 cycle in `clk_dst`.
Synthesis Constraints: Consecutive pulses must be spaced far enough apart to allow toggle completion in the slow domain.
Architectural Deep Dive & Implementation Walkthrough
Common RTL Designer Pitfalls
['Sending a second pulse before the first pulse has been sampled in the destination domain, causing pulse collision/loss.', 'Using a simple edge detector (`dst_q2 & ~dst_q3`) instead of XOR (`dst_q2 ^ dst_q3`), which misses every alternate pulse.']
Silicon & Hardware Engineering Notes
Ensure the pulse rate in the fast domain is less than twice the period of the slow clock domain, or use an asynchronous handshake/FIFO.
Starter RTL Code
module top_module(
input clk_src,
input areset_src_n,
input pulse_src,
input clk_dst,
input areset_dst_n,
output pulse_dst
);
// Toggle Pulse Synchronizer across clock domains
endmodule
Verified Reference Solution
🔒 Reveal Verified Reference RTL Solution
module top_module(
input clk_src,
input areset_src_n,
input pulse_src,
input clk_dst,
input areset_dst_n,
output pulse_dst
);
reg src_toggle;
// Step 1: In source domain, toggle on each pulse
always @(posedge clk_src or negedge areset_src_n) begin
if (!areset_src_n)
src_toggle <= 1'b0;
else if (pulse_src)
src_toggle <= ~src_toggle;
end
// Step 2: Synchronize toggle level across CDC into clk_dst using 2 flops
reg dst_q1, dst_q2, dst_q3;
always @(posedge clk_dst or negedge areset_dst_n) begin
if (!areset_dst_n) begin
dst_q1 <= 1'b0;
dst_q2 <= 1'b0;
dst_q3 <= 1'b0;
end else begin
dst_q1 <= src_toggle;
dst_q2 <= dst_q1;
dst_q3 <= dst_q2;
end
end
// Step 3: Edge detector (XOR detects both 0->1 and 1->0 toggle transitions)
assign pulse_dst = dst_q2 ^ dst_q3;
endmodule
Related RTL Problems in Level 4
- Two-Flop Synchronizer — Single-Bit CDC — Design a 2-flip-flop synchronizer to safely pass a single-bit control signal from an asynchronous source into the destination clock domain clk_dst.
- Gray Code Counter — Gray Encoding — Implement a 4-bit Gray code counter that advances by exactly one bit per transition: 0000, 0001, 0011, 0010, 0110, 0111, 0101, 0100...
- Asynchronous FIFO Pointer Synchronization — Multi-Clock Design — Convert a 4-bit write pointer to Gray code in clk_wr, synchronize it across clock domains into clk_rd using a 2-flop synchronizer, and generate a safe rd_empty flag.
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Frequently Asked Questions
What does Pulse Synchronizer — Clock-Domain Crossing require?
Design a Toggle-based Pulse Synchronizer to transfer a single-cycle pulse from a fast clock domain (clk_src) to a slow destination domain (clk_dst). Implement it as Verilog module top_module matching the listed ports.
Is this design combinational or sequential?
Tags: cdc, industry-rtl, arbiters, clock-domain-crossing, hard, pulse-synchronizers. If a clock signal is present in the port table, implement it as sequential logic; otherwise, use continuous assignments or combinational blocks.
How is my solution graded?
A hidden SystemVerilog testbench simulates your module in the cloud judge. You pass when all directed corner cases match the golden model and the VCD timing waveform matches the contract.
How does this challenge help with semiconductor interviews?
Technical interviewers at NVIDIA, Qualcomm, Apple, and Intel routinely ask candidates to code, debug, and explain the timing waveforms of Pulse Synchronizer — Clock-Domain Crossing to assess real-world synthesizability and race-condition awareness.