Hamming Distance Calculator

Verilog problems / Fun & Games

What you must build

Count how many bit positions differ between two 8-bit values — the core distance metric behind error-correcting codes like Hamming(7,4).

Engineers use “Hamming Distance Calculator” as a building block in fun & games. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is an introductory kata. Prefer a clear continuous assignment or a small combinational always block. Name the module top_module and keep the port list identical to the table — the hidden testbench instantiates that name.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  [7:0] a,
  input  [7:0] b,
  output [3:0] distance
);

  // Your code here — distance = popcount(a ^ b).

endmodule

Why this shows up in interviews

Hamming Distance Calculator sits under Fun & Games (combinational, error-correction). Concept: XOR marks exactly the bit positions where two values disagree, so the Hamming distance is simply the popcount of a^b : diff=a^b; distance=diff[0]+diff[1]+...+diff[7]; . Swapping XOR for AND is an easy bitwise mix-up that produces a real (but wrong) number instead of an obvious error — a&b counts bits that are set in both operands, which is an entirely different quantity that happens to equal zero whenever the two values share no 1-bits at all, masking the bug on plenty of otherwise-reasonable test inputs.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

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