RTL Problems / Level 2 · Sequential Logic
What You Will Learn
By solving D Flip-Flop — Positive-Edge-Triggered Storage, you will acquire core industry skills:
- Synthesizable hardware modeling in standard Verilog-2001 / SystemVerilog.
- Correct handling of interface port contracts, edge-triggered clocks, and active-low/high resets.
- Simulation waveform interpretation and debugging using timing diagrams (VCD traces).
- Architectural avoidance of timing violations, glitching hazards, and synthesis warnings.
Problem Statement & Requirements
Implement a basic 1-bit positive-edge-triggered D flip-flop without reset.
Hardware design teams at leading semiconductor firms evaluate these exact port contracts, race-condition assertions, and corner cases during technical design reviews and ASIC engineer interviews.
Prerequisites: Clock signals, posedge sensitivity lists, procedural `always @(posedge clk)` blocks.
Port List & Interface Timing
The hidden testbench instantiates top_module. Module port names and bit-widths must match the interface contract exactly:
| Name | Dir | Width | Description |
|---|---|---|---|
clk | input | 1 | Master positive-edge clock |
d | input | 1 | Data input |
q | output | 1 | Registered data output |
Timing Constraints & Synthesizable RTL Rules
Timing Contract: Input `d` sampled at `posedge clk`. Output `q` updates after clock-to-q delay $t_{c-q}$.
Synthesis Constraints: Must use non-blocking assignment (`<=`) inside `always @(posedge clk)`.
Architectural Deep Dive & Implementation Walkthrough
Common RTL Designer Pitfalls
['Using blocking assignment (`=`) instead of non-blocking (`<=`), which causes simulation race conditions.', 'Adding `d` to the sensitivity list (`always @(posedge clk or d)`), which describes an illegal asynchronous register.']
Silicon & Hardware Engineering Notes
Standard-cell DFFs exhibit setup time ($t_{su}$) and hold time ($t_h$) constraints relative to the clock edge. Violating these causes metastability.
Starter RTL Code
module top_module(
input clk,
input d,
output reg q
);
// Positive-edge-triggered D flip-flop
endmodule
Verified Reference Solution
🔒 Reveal Verified Reference RTL Solution
module top_module(
input clk,
input d,
output reg q
);
always @(posedge clk) begin
q <= d;
end
endmodule
Related RTL Problems in Level 2
- D Flip-Flop with Asynchronous Reset — Reset Behavior — Design a D flip-flop with active-low asynchronous reset (areset_n). Reset forces q to 0 immediately, independent of clk.
- D Flip-Flop with Synchronous Reset — Clocked Reset — Implement a D flip-flop with active-high synchronous reset (sync_rst). The reset takes effect only on the rising clock edge.
- D Flip-Flop with Enable — Conditional Register Update — Design a D flip-flop with active-high synchronous enable (en) and active-low asynchronous reset (areset_n).
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Frequently Asked Questions
What does D Flip-Flop — Positive-Edge-Triggered Storage require?
Implement a basic 1-bit positive-edge-triggered D flip-flop without reset. Implement it as Verilog module top_module matching the listed ports.
Is this design combinational or sequential?
Tags: sequential, fsm, counters, medium, flip-flops-&-latches. If a clock signal is present in the port table, implement it as sequential logic; otherwise, use continuous assignments or combinational blocks.
How is my solution graded?
A hidden SystemVerilog testbench simulates your module in the cloud judge. You pass when all directed corner cases match the golden model and the VCD timing waveform matches the contract.
How does this challenge help with semiconductor interviews?
Technical interviewers at NVIDIA, Qualcomm, Apple, and Intel routinely ask candidates to code, debug, and explain the timing waveforms of D Flip-Flop — Positive-Edge-Triggered Storage to assess real-world synthesizability and race-condition awareness.