RTL Problems / Level 6 · Advanced RTL & Protocol Design
What You Will Learn
By solving 4-Channel Packet-Locked Chiplet Scheduler, you will acquire core industry skills:
- Synthesizable hardware modeling in standard Verilog-2001 / SystemVerilog.
- Correct handling of interface port contracts, edge-triggered clocks, and active-low/high resets.
- Simulation waveform interpretation and debugging using timing diagrams (VCD traces).
- Architectural avoidance of timing violations, glitching hazards, and synthesis warnings.
Problem Statement & Requirements
Design a 4-channel packet scheduler ensuring complete packet atomicity and fair round-robin scheduling across chiplet ingress queues.
Hardware design teams at leading semiconductor firms evaluate these exact port contracts, race-condition assertions, and corner cases during technical design reviews and ASIC engineer interviews.
Prerequisites: Packet boundary tracking (SOP/EOP), packet-level arbitration, round-robin fairness.
Port List & Interface Timing
The hidden testbench instantiates top_module. Module port names and bit-widths must match the interface contract exactly:
| Port | Dir | Width | Description |
|---|---|---|---|
clk, rst_n | input | 1 | Clock and active-low synchronous reset |
ch_valid[3:0], ch_ready[3:0] | in/out | 4 | Channel flow control handshake |
ch_sop[3:0], ch_eop[3:0] | input | 4 | Packet boundary indicators per channel |
ch_data[127:0] | input | 128 | Packed channel data (ch0=[31:0], ch1=[63:32], ch2=[95:64], ch3=[127:96]) |
out_valid, out_ready | out/in | 1 | Scheduled egress handshake |
out_sop, out_eop, out_data[31:0] | output | 1, 1, 32 | Egress packet stream framing and data |
Timing Constraints & Synthesizable RTL Rules
Timing Contract: Clocked on posedge clk with active-low rst_n. Grant locked strictly between SOP and EOP. Priority pointer advances on EOP transfer.
Synthesis Constraints: Zero packet interleaving. Synthesizable Verilog-2001.
Architectural Deep Dive & Implementation Walkthrough
Packet Framing and Head-of-Line Blocking
Packet multiplexers in PCIe, Ethernet, and UCIe architectures must guarantee packet atomicity: once a packet's Start of Packet (SOP) is emitted, no other channel may transmit until the End of Packet (EOP) is acknowledged.
Arbitration and Locking Cycle
- Channel Selection: The arbiter identifies requesting channels that have
SOP = 1. It uses round-robin fairness to select the next winner. - Atomicity Lock: The arbiter enters the locked state, routing only the winning channel's data beats to the egress port.
- Release: When
EOPhandshakes with the consumer, the lock drops and the priority pointer advances.
Common RTL Designer Pitfalls
Allowing non-SOP beats to trigger arbitration, or failing to lock the grant when downstream pauses (out_ready = 0).
Silicon & Hardware Engineering Notes
Advanced NoCs use virtual channels (VCs) to prevent head-of-line blocking when one destination is congested.
Starter RTL Code
module top_module (
input wire clk,
input wire rst_n,
input wire [3:0] ch_valid,
output reg [3:0] ch_ready,
input wire [3:0] ch_sop,
input wire [3:0] ch_eop,
input wire [127:0] ch_data,
output reg out_valid,
input wire out_ready,
output reg out_sop,
output reg out_eop,
output reg [31:0] out_data
);
// Implement 4-channel packet-locked scheduler:
// 1. When unlocked, arbitrate among active channels with ch_sop = 1 using round-robin.
// 2. Lock to the granted channel until out_valid && out_ready && out_eop.Verified Reference Solution
🔒 Reveal Verified Reference RTL Solution
module top_module (
input wire clk,
input wire rst_n,
input wire [3:0] ch_valid,
output reg [3:0] ch_ready,
input wire [3:0] ch_sop,
input wire [3:0] ch_eop,
input wire [127:0] ch_data,
output reg out_valid,
input wire out_ready,
output reg out_sop,
output reg out_eop,
output reg [31:0] out_data
);
reg [1:0] active_ch;
reg [1:0] rr_ptr;
reg locked;
wire [31:0] ch_in [0:3];
assign ch_in[0] = ch_data[31:0];
assign ch_in[1] = ch_data[63:32];
assign ch_in[2] = ch_data[95:64];
assign ch_in[3] = ch_data[127:96];
// Pick next candidate channel
reg [1:0] next_pick;
reg has_candidate;
always @(*) begin
has_candidate = 1'b0;
next_pick = rr_ptr;
if (ch_valid[rr_ptr] && ch_sop[rr_ptr]) begin
has_candidate = 1'b1;
next_pick = rr_ptr;
end else if (ch_valid[(rr_ptr + 2'd1) & 2'd3] && ch_sop[(rr_ptr + 2'd1) & 2'd3]) begin
has_candidate = 1'b1;
next_pick = (rr_ptr + 2'd1) & 2'd3;
end else if (ch_valid[(rr_ptr + 2'd2) & 2'd3] && ch_sop[(rr_ptr + 2'd2) & 2'd3]) begin
has_candidate = 1'b1;
next_pick = (rr_ptr + 2'd2) & 2'd3;
end else if (ch_valid[(rr_ptr + 2'd3) & 2'd3] && ch_sop[(rr_ptr + 2'd3) & 2'd3]) begin
has_candidate = 1'b1;
next_pick = (rr_ptr + 2'd3) & 2'd3;
end
end
// Combinational output muxing
always @(*) begin
ch_ready = 4'b0000;
if (locked) begin
out_valid = ch_valid[active_ch];
out_sop = ch_sop[active_ch];
out_eop = ch_eop[active_ch];
out_data = ch_in[active_ch];
ch_ready[active_ch] = out_ready;
end else if (has_candidate) begin
out_valid = ch_valid[next_pick];
out_sop = ch_sop[next_pick];
out_eop = ch_eop[next_pick];
out_data = ch_in[next_pick];
ch_ready[next_pick] = out_ready;
end else begin
out_valid = 1'b0;
out_sop = 1'b0;
out_eop = 1'b0;
out_data = 32'h0;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
active_ch <= 2'd0;
rr_ptr <= 2'd0;
locked <= 1'b0;
end else begin
if (!locked) begin
if (has_candidate) begin
active_ch <= next_pick;
if (out_valid && out_ready && out_eop) begin
// Single-beat packet (SOP && EOP same beat)
locked <= 1'b0;
rr_ptr <= (next_pick + 2'd1) & 2'd3;
end else if (out_valid && out_ready) begin
locked <= 1'b1;
end
end
end else begin
if (out_valid && out_ready && out_eop) begin
locked <= 1'b0;
rr_ptr <= (active_ch + 2'd1) & 2'd3;
end
end
end
end
endmodule
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Frequently Asked Questions
What does 4-Channel Packet-Locked Chiplet Scheduler require?
Design a 4-channel packet scheduler ensuring complete packet atomicity and fair round-robin scheduling across chiplet ingress queues. Implement it as Verilog module top_module matching the listed ports.
Is this design combinational or sequential?
Tags: advanced-rtl, arbitration-and-interconnect, systemverilog, asic, fpga. If a clock signal is present in the port table, implement it as sequential logic; otherwise, use continuous assignments or combinational blocks.
How is my solution graded?
A hidden SystemVerilog testbench simulates your module in the cloud judge. You pass when all directed corner cases match the golden model and the VCD timing waveform matches the contract.
How does this challenge help with semiconductor interviews?
Technical interviewers at NVIDIA, Qualcomm, Apple, and Intel routinely ask candidates to code, debug, and explain the timing waveforms of 4-Channel Packet-Locked Chiplet Scheduler to assess real-world synthesizability and race-condition awareness.