easy 10 pts Solved

Rock Paper Scissors Lizard Spock

Judge a round of the 5-way expanded rock-paper-scissors from The Big Bang Theory — each move beats exactly two of the other four, so the usual 3-way rule table isn't enough.

Verilog problems / Fun & Games

What you must build

Judge a round of the 5-way expanded rock-paper-scissors from The Big Bang Theory — each move beats exactly two of the other four, so the usual 3-way rule table isn't enough.

Engineers use “Rock Paper Scissors Lizard Spock” as a building block in fun & games. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Concept: Encode each player's move as 0=Rock, 1=Paper, 2=Scissors, 3=Lizard, 4=Spock. Every move beats exactly two others (Rock beats Scissors and Lizard; Paper beats Rock and Spock; Scissors beats Paper and Lizard; Lizard beats Spock and Paper; Spock beats Scissors and Rock) — so the cleanest implementation is a direct lookup of p1's beats-list against p2, then the reverse check if that fails. A single wrong entry in that beats-list (say, listing Paper instead of Scissors as one of Rock's victims) is a real, easy-to-make copy-paste slip — it still compiles and handles most matchups correctly, but silently flips the outcome for that one specific matchup.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

NameDirWidthDescription
p1input3Player 1's move (0=Rock,1=Paper,2=Scissors,3=Lizard,4=Spock)
p2input3Player 2's move, same encoding
winneroutput20=tie, 1=player 1 wins, 2=player 2 wins

How to approach this kata

This is a medium kata: you will need sequential logic or a small FSM. Decide what is registered versus combinational before you type. Reset polarity and clock edge must match the spec; the judge will fail you on the first mismatched cycle.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  [2:0] p1,
  input  [2:0] p2,
  output [1:0] winner
);

  // Your code here — 0=Rock,1=Paper,2=Scissors,3=Lizard,4=Spock.
  // Each move beats exactly two others. winner: 0=tie, 1=p1 wins, 2=p2 wins.

endmodule

Why this shows up in interviews

Rock Paper Scissors Lizard Spock sits under Fun & Games (combinational, game-logic). Concept: Encode each player's move as 0=Rock, 1=Paper, 2=Scissors, 3=Lizard, 4=Spock. Every move beats exactly two others (Rock beats Scissors and Lizard; Paper beats Rock and Spock; Scissors beats Paper and Lizard; Lizard beats Spock and Paper; Spock beats Scissors and Rock) — so the cleanest implementation is a direct lookup of p1's beats-list against p2, then the reverse check if that fails. A single wrong entry in that beats-list (say, listing Paper instead of Scissors as one of Rock's victims) is a real, easy-to-make copy-paste slip — it still compiles and handles most matchups correctly, but silently flips the outcome for that one specific matchup.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

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FAQ

What does this problem require?

What does the Rock Paper Scissors Lizard Spock problem ask for? Judge a round of the 5-way expanded rock-paper-scissors from The Big Bang Theory — each move beats exactly two of the other four, so the usual 3-way rule table isn't enough. Implement it as Verilog module top_module with the listed ports.

Combinational or sequential?

Is Rock Paper Scissors Lizard Spock combinational or sequential? Tags: combinational, game-logic. Follow the clock/reset ports if they appear in the table; if there is no clock, use continuous assignment or combinational always @(*).

How does the auto-grader work?

How is Rock Paper Scissors Lizard Spock graded? A hidden SystemVerilog/Verilog testbench in the EcrioniX judge simulates your module in the browser. You pass when every directed vector matches, including the waveform contract shown on this page.

Write a module named top_module matching the ports below exactly.
Expected waveform
Your solution
Judge output
// Output appears after you run tests.