Slot Machine Jackpot Detector

Verilog problems / Fun & Games

What you must build

Judge a 3-reel slot machine spin: jackpot when all three reels match, a smaller near-miss flag when exactly two do.

Engineers use “Slot Machine Jackpot Detector” as a building block in fun & games. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is an introductory kata. Prefer a clear continuous assignment or a small combinational always block. Name the module top_module and keep the port list identical to the table — the hidden testbench instantiates that name.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  [2:0] reel1,
  input  [2:0] reel2,
  input  [2:0] reel3,
  output jackpot,
  output two_match
);

  // Your code here — jackpot if all three reels are equal; two_match if any pair matches but not all three.

endmodule

Why this shows up in interviews

Slot Machine Jackpot Detector sits under Fun & Games (combinational, comparator). Concept: A true jackpot requires all three reels to agree: jackpot=(reel1==reel2)&&(reel2==reel3); , with two_match catching the near-miss case where only some pair agrees. The easy mistake is checking only one pair (say reel1==reel2 ) and calling that the jackpot condition — it correctly fires when all three genuinely match, but it also fires whenever just the first two happen to match and the third is completely different, awarding a jackpot for what should only ever be a two-reel near-miss.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

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