Space Invaders Collision Detector

Verilog problems / Fun & Games

What you must build

Detect whether a bullet hits an alien: a classic range-overlap check dressed up as retro arcade collision logic.

Engineers use “Space Invaders Collision Detector” as a building block in fun & games. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is an introductory kata. Prefer a clear continuous assignment or a small combinational always block. Name the module top_module and keep the port list identical to the table — the hidden testbench instantiates that name.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  [3:0] bullet_x,
  input  [3:0] alien_x,
  input  [2:0] alien_width,
  output hit
);

  // Your code here — hit if alien_x <= bullet_x < alien_x + alien_width.

endmodule

Why this shows up in interviews

Space Invaders Collision Detector sits under Fun & Games (combinational, comparator). Concept: The alien occupies a run of cells from alien_x up to (but not including) alien_x+alien_width ; the bullet hits when its position falls anywhere in that half-open range: hit = (bullet_x>=alien_x) && (bullet_x<alien_x+alien_width); . Using <= instead of < for the upper bound is a classic off-by-one in collision detection — it counts one extra cell just past the alien's actual right edge as a hit, so a bullet that should whiff right next to the alien registers a phantom collision instead.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

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