SPI Mode Selector (CPOL/CPHA)

Verilog problems / Protocols & Interfaces

What you must build

Decode SPI's 4 clocking modes from CPOL and CPHA into the two facts a controller actually needs: what the clock idles at, and which edge samples data.

Engineers use “SPI Mode Selector (CPOL/CPHA)” as a building block in protocols & interfaces. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is an introductory kata. Prefer a clear continuous assignment or a small combinational always block. Name the module top_module and keep the port list identical to the table — the hidden testbench instantiates that name.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  cpol,
  input  cpha,
  output idle_clock,
  output sample_edge
);

  // Your code here — idle_clock = cpol; sample_edge = cpol ^ cpha.

endmodule

Why this shows up in interviews

SPI Mode Selector (CPOL/CPHA) sits under Protocols & Interfaces (combinational, protocol). Concept: CPOL sets the clock's idle level directly ( idle_clock=cpol ). Which edge samples data is a clean XOR of the two: sample_edge = cpol ^ cpha (0=rising, 1=falling) — a fact worth knowing cold rather than re-deriving from the mode table every time. Swapping that XOR for an AND is a very plausible boolean slip: it happens to agree with the correct answer for modes 0 and... no, it actually gets 3 of the 4 modes wrong, because AND and XOR only ever agree when both inputs are 0.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• CRC-8 Generator (poly 0x07) — Compute an 8-bit CRC over a byte using the classic 0x07 polynomial (CRC-8-CCITT) — the same bit-serial algorithm behind this catalog's CRC-4, scaled up to a full byte.
• APB Slave Register Interface — A minimal AMBA APB slave: 4 registers, zero wait states — and the two-phase setup/access handshake that decides exactly when a write is allowed to land.
• AXI4-Lite Write Channel FSM — Accept an address+data write beat, then hold the response channel until the master acknowledges — the handshake FSM behind every AXI4-Lite peripheral.
• AXI4-Lite Read Channel FSM — The read-side twin of this catalog's AXI4-Lite write FSM: accept an address, then hold the data response until the master accepts it.

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