Advanced
L6
⏱️ 6–8 weeks
Protocol RTL Design
Implement industry-standard AMBA APB, AXI4-Lite, AXI-Stream, and UART/SPI communication interfaces with backpressure.
Valid-Ready Flow Control & Handshake Contracts
Master strict AMBA valid-ready handshake rules: valid must remain asserted until ready is granted.
Decoupled handshakingCombinational dependency rulesBackpressure generation
Practice RTL Problems (2)
Skid Buffers & Register Slices
Break long combinational ready backpressure timing paths while preserving 100% throughput.
Forward register sliceBackward registered ready2-slot primary and skid buffers
Practice RTL Problems (3)
APB Slave Controller & Phase FSM
Implement standard 2-phase APB transfers across IDLE, SETUP, and ACCESS states.
PSEL & PENABLE timingPWRITE read/write distinctionPADDR decoding
Practice RTL Problems (2)
APB Wait States & PSLVERR Handling
Implement slave-driven wait-state insertion using PREADY and error reporting via PSLVERR.
PREADY deassertionWait state insertionUnmapped address PSLVERR reporting
Practice RTL Problems (1)
Memory-Mapped APB Register Bank
Synthesize standard peripheral register sets: CTRL, STATUS, SCRATCH, and INTERRUPT_EN.
Memory mappingRead-only vs Read-Write registersWrite-strobe bit enables
Practice RTL Problems (1)
APB Master Transaction Controller
Design an APB master state machine translating CPU core read/write requests into compliant APB phases.
Core request latchingSETUP to ACCESS phase timingSlave response completion
Practice RTL Problems (2)
AXI Write Channel Handshake Controller
Implement decoupled AW (address) and W (data) channels with write response (B channel) tracking.
Decoupled address/data timingWLAST burst terminationBRESP status decoding
Practice RTL Problems (2)
AXI Read Channel Burst Controller
Coordinate AR (read address) issue with multi-beat R (read data) burst responses and RLAST flags.
ARVALID / ARREADY handshakeMulti-beat burst streamingRLAST flag assertions
Practice RTL Problems (2)
AXI-Stream Arbitration & Packet Framing
Arbitrate among multi-channel AXI-Stream producers while maintaining packet atomicity between TLAST beats.
TVALID, TREADY, TDATA, TLASTRound-robin stream arbitrationPacket-boundary locking
Practice RTL Problems (2)
UART & SPI Serial Controllers
Implement UART transmit/receive state machines with baud rate generation and SPI mode controllers.
Baud rate divisionStart/Stop bit framingSPI CPOL/CPHA modesFull-duplex shift register
Practice RTL Problems (4)
Why Master Protocol RTL Design?
Design synthesizable masters, slaves, and interconnect routers adhering strictly to AMBA and serial protocol specifications. Engineers who excel in this curriculum consistently outperform in technical interviews at semiconductor leaders such as NVIDIA, Qualcomm, Apple, and Intel because this roadmap focuses on synthesizability, edge-case assertions, and real simulation waveforms rather than purely theoretical textbook logic.
Recommended Learning Methodology
- Step 1 — Understand the Concept: Read each module's core objectives and referenced EcrioniX guide.
- Step 2 — Code the RTL: Open each practice challenge and implement
top_module matching the exact ports and timing contract.
- Step 3 — Inspect Waveforms: Run the remote cloud simulator to generate timing waveforms (VCD). Compare your signal transitions with the golden WaveDrom contract.
- Step 4 — Review Explanations: Even after passing, review the editorial notes and hardware considerations to understand ASIC synthesis tradeoffs.
Frequently Asked Questions
What tools do I need for this roadmap?
None! All simulation testbenches run in the browser using our remote Icarus Verilog runner with automated waveform generation.
Are the reference solutions accessible?
Yes. Reference solutions are protected in an expandable solution drawer. We strongly encourage attempting and simulating your own RTL first.