RTL Problems / Level 6 · RTL Protocol Design
What You Will Learn
By solving UART 8-N-1 Serial Receiver, you will acquire core industry skills:
- Synthesizable hardware modeling in standard Verilog-2001 / SystemVerilog.
- Correct handling of interface port contracts, edge-triggered clocks, and active-low/high resets.
- Simulation waveform interpretation and debugging using timing diagrams (VCD traces).
- Architectural avoidance of timing violations, glitching hazards, and synthesis warnings.
Problem Statement & Requirements
Demodulate asynchronous serial data: detect the start bit (0), sample 8 data bits LSB first, verify the stop bit (1), and output valid parallel data.
Hardware design teams at leading semiconductor firms evaluate these exact port contracts, race-condition assertions, and corner cases during technical design reviews and ASIC engineer interviews.
Port List & Interface Timing
The hidden testbench instantiates top_module. Module port names and bit-widths must match the interface contract exactly:
| Name | Dir | Width | Description |
|---|---|---|---|
| clk | input | 1 | Baud-rate sample clock |
| rst_n | input | 1 | Active-low reset |
| rx | input | 1 | Serial data input line |
| data_out | output | 8 | Deserialized parallel 8-bit byte |
| valid | output | 1 | 1-cycle strobe indicating complete byte received |
Timing Constraints & Synthesizable RTL Rules
Timing Contract: Strict synchronous timing aligned to posedge clk or zero-delay combinational propagation.
Synthesis Constraints: Synthesizable Verilog-2001. No # delays in synthesizable RTL.
Starter RTL Code
module top_module (
input wire clk,
input wire rst_n,
input wire rx,
output reg [7:0] data_out,
output reg valid
);
// Your code here
endmodule
Related RTL Problems in Level 6
- Manchester Encoder — Combine a data bit with the clock to produce a Manchester-encoded line signal — the self-clocking encoding used in classic Ethernet and RFID.
- Manchester Decoder — Recover the original data bit from a Manchester-encoded line signal — the exact inverse of the Manchester Encoder problem.
- Quadrature Rotary Encoder Decoder — Decode the two-phase A/B signal from a real rotary knob or mouse wheel into a direction and position count — sample B on every rising edge of A.
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Frequently Asked Questions
What does UART 8-N-1 Serial Receiver require?
Demodulate asynchronous serial data: detect the start bit (0), sample 8 data bits LSB first, verify the stop bit (1), and output valid parallel data. Implement it as Verilog module top_module matching the listed ports.
Is this design combinational or sequential?
Tags: protocols, uart, fsm, serial. If a clock signal is present in the port table, implement it as sequential logic; otherwise, use continuous assignments or combinational blocks.
How is my solution graded?
A hidden SystemVerilog testbench simulates your module in the cloud judge. You pass when all directed corner cases match the golden model and the VCD timing waveform matches the contract.
How does this challenge help with semiconductor interviews?
Technical interviewers at NVIDIA, Qualcomm, Apple, and Intel routinely ask candidates to code, debug, and explain the timing waveforms of UART 8-N-1 Serial Receiver to assess real-world synthesizability and race-condition awareness.