Complete guide to PCIe power delivery — slot limits, connectors, ASPM power states, TLP/DLLP protocol layers, and PCIe Gen5 600W power delivery.
PCIe slots deliver power directly from the motherboard through the slot connector. Power limits depend on slot width (lane count):
| Connector | Pins | Power | Voltage | Typical Use |
|---|---|---|---|---|
| 6-pin PCIe | 3×12V + 3×GND | 75W | 12V | Mid-range GPUs (GTX 1660, RX 6600) |
| 8-pin PCIe | 2×12V + 1×12V + 5×GND | 150W | 12V | High-end GPUs (RTX 3080, RX 6800 XT) |
| 2×8-pin | Two 8-pin | 300W | 12V | RTX 3090, RX 6900 XT |
| 12VHPWR 16-pin | 12×12V + 4 sense | 600W | 12V | RTX 4090, NVIDIA H100 PCIe |
12VHPWR connector safety: The PCIe Gen5 16-pin (12VHPWR) connector delivering 600W caused early issues with melting when adapters were not fully seated. The 4 sense/sideband pins negotiate power delivery — the card only draws full power when the connector is properly detected as seated. Never use adapter cables at a sharp bend angle.
PCIe is a layered, point-to-point serial protocol. Unlike PCI (shared bus), every PCIe device has a dedicated link to the root complex. The protocol has three main layers:
| Layer | Packet Type | Functions |
|---|---|---|
| Transaction Layer | TLP (Transaction Layer Packet) | Memory Read/Write, I/O R/W, Config R/W, Message, Completion. Carries actual data payloads. |
| Data Link Layer | DLLP (Data Link Layer Packet) | ACK/NAK (reliability), Flow Control (credits), Power Management, Link Initialization |
| Physical Layer | Ordered Sets | SerDes, 8b/10b (Gen1/2) or 128b/130b (Gen3+) encoding, LTSSM link training, lane equalization |
| TLP Type | Use | Has Data? |
|---|---|---|
| MRd (Memory Read) | Read N bytes from memory address | No (request) |
| MWr (Memory Write) | Write data to memory address | Yes |
| CplD (Completion with Data) | Reply to a read request, carries read data | Yes |
| Cpl (Completion) | Reply to a write (non-posted requires completion) | No |
| IORd / IOWr | Legacy I/O space access | No / Yes |
| CfgRd / CfgWr | Configuration space (PCIe registers) | No / Yes |
| Msg | Interrupts (MSI-X), power management events, vendor-specific | Optional |
ASPM (Active State Power Management) allows PCIe links to enter low-power states automatically when idle, without OS involvement. States are negotiated during link training.
| State | Description | Entry Latency | Power Saving | Clock |
|---|---|---|---|---|
| L0 | Fully active — data transfer in progress | — | 0% | Running |
| L0s | Electrical idle, fast wake — receiver still powered | ~70ns exit | 10–15% | Running |
| L1 | Deep idle — link clock off, PLL still on | ~4µs exit | ~50% | Off |
| L1.1 | L1 substate — PLL off, ref clock from common clock | ~10µs exit | ~65% | Off |
| L1.2 | L1 substate — regulator off, deepest ASPM state | ~130µs exit | ~85% | Off |
| L2 | Soft power-off — main power removed, aux power remains | ~10ms resume | ~95% | Off |
| L3 | Full power-off — no power | Cold boot | 100% | Off |
ASPM L1.2 in mobile: L1.2 is the most important state for laptop and mobile SoC power savings. NVMe SSDs, PCIe-based WiFi, and Thunderbolt controllers all use L1.2 during idle to achieve sub-milliwatt link power consumption. This is critical for battery life on laptops.
| Generation | Speed/Lane | x16 BW | Encoding | Max Power (slot) | Year |
|---|---|---|---|---|---|
| PCIe Gen 1 | 2.5 GT/s | 4 GB/s | 8b/10b | 75W | 2003 |
| PCIe Gen 2 | 5 GT/s | 8 GB/s | 8b/10b | 75W | 2007 |
| PCIe Gen 3 | 8 GT/s | 16 GB/s | 128b/130b | 75W | 2010 |
| PCIe Gen 4 | 16 GT/s | 32 GB/s | 128b/130b | 75W | 2019 |
| PCIe Gen 5 | 32 GT/s | 64 GB/s | 128b/130b | 75W + 600W (16-pin) | 2022 |
| PCIe Gen 6 | 64 GT/s | 128 GB/s | PAM4 + FLIT | TBD | 2023+ |
Note: Each PCIe generation doubles the per-lane bandwidth while keeping the same physical slot connector. A PCIe Gen 4 x4 slot (common for NVMe) delivers the same bandwidth as a Gen 3 x8 slot. Backward compatibility is maintained — a Gen 5 card in a Gen 3 slot falls back to Gen 3 speeds.
For VLSI engineers designing SoCs with PCIe endpoints or root complexes:
A PCIe x16 slot provides up to 75W directly from the motherboard. GPUs needing more use auxiliary connectors: 6-pin (+75W), 8-pin (+150W), 16-pin/12VHPWR (+600W). Total GPU power = slot power + auxiliary connector power.
ASPM (Active State Power Management) lets the PCIe link enter low-power states (L0s, L1, L1.1, L1.2) automatically when idle — without OS intervention. L1.2 saves up to 85% link power and is critical for laptop battery life.
TLP (Transaction Layer Packet) carries actual data: Memory Read/Write, Config, Completion. DLLP (Data Link Layer Packet) handles reliability: ACK/NAK, flow control credits, power management. TLPs are the payload; DLLPs manage the link. Both ride on top of the Physical Layer SerDes.
The 12VHPWR 16-pin connector (introduced with PCIe Gen 5) delivers up to 600W at 12V. It replaced multiple 8-pin connectors. Used by NVIDIA RTX 4090 (450W), NVIDIA H100 PCIe (350W). The 4 sense pins negotiate actual power delivery with the PSU.
"PCIe e-delivery" refers to PCIe electronic/power delivery mechanisms — how power is electronically delivered to PCIe cards via slot pins and auxiliary connectors. It encompasses ASPM power state management and the power delivery specification for PCIe cards.