Before a single standard cell is placed, the physical canvas must be set up correctly. A bad floorplan echoes through every downstream step — causing routing congestion, timing failures, and IR drop that no optimizer can fix.
The first decision in physical design is: how big does the die need to be? Die size directly impacts cost — silicon area is money. The starting point is the utilization factor, which controls how densely standard cells fill the core area.
The formula is straightforward:
| Utilization % | Typical use case | Risk |
|---|---|---|
| 40–55% | High-performance designs (CPU, GPU cores) | Large die, high cost |
| 60–70% | Standard SoC blocks, most ASIC designs | Balanced — preferred target |
| 75–85% | Area-optimized, cost-sensitive designs | Routing congestion risk, hard to fix |
| >85% | Avoid — routing becomes impossible | DRC violations, open nets |
The synthesis tool reports total cell area. Add 20–30% overhead for filler cells, decoupling caps, and routing resource. Always include macro areas (SRAM, ROM, IP blocks) separately — they are fixed-size and not part of the utilization calculation for standard cells.
# TCL: Create floorplan with explicit die/core dimensions create_floorplan \ -die_area {0 0 2000 1500} \ -core_area {50 50 1950 1450} \ -core_utilization 0.65 \ -core_aspect_ratio 1.0 \ -core_to_boundary_distance {20 20 20 20} # die_area: {llx lly urx ury} in microns # core_area: standard cell placement region (inside power ring) # Or let the tool compute die from utilization target: create_floorplan \ -core_utilization 0.65 \ -core_aspect_ratio 1.2 \ -core_to_boundary_distance {15 15 15 15}
The aspect ratio (height/width) of the core affects routing efficiency. A ratio of 1.0 (square) is generally optimal — it minimizes the maximum wire length for any net. Very wide or very tall dies create long horizontal or vertical wires on one axis, wasting routing tracks.
The core area is where standard cells and macros are placed. The die area includes:
Large macros (SRAMs, ROMs, analog blocks, hard IPs) must be placed first — they are immovable boulders that the rest of the design routes around. Poor macro placement is the most common cause of routing congestion in real chips.
An SRAM connected to a CPU data bus should sit adjacent to the CPU core, minimizing wire length for the wide data bus (32–512 bits). Long bus wires add significant routing congestion and timing delay.
Macros placed in the middle of the die create routing channels — corridors that signals must pass through. If a macro blocks these channels, thousands of nets must detour, causing congestion hotspots. Push macros to the floorplan edges or corners.
Every macro needs a halo — a keepout margin around it where no standard cells are placed. Halos prevent timing issues from coupling, allow power strap routing around the macro, and provide space for the macro's input/output pin access routes. Typical halo: 5–15 µm.
Macro edges should snap to the routing grid (usually the metal-1 pitch). Mis-aligned macros create fractional-track gaps that routers cannot use, wasting routing resources near the macro boundary.
# Place specific macros at fixed locations place_macro -inst SRAM_0 -location {100 80} -orient R0 place_macro -inst SRAM_1 -location {100 500} -orient R0 place_macro -inst CPU_CORE -location {400 200} -orient R0 # Define halos around macros create_place_halo -halo_deltas {10 10 10 10} \ -inst [get_cells {SRAM_0 SRAM_1}] # Create placement blockage in specific region create_placement_blockage \ -bbox {0 0 50 1500} \ -type hard # Prevents std cells within 50µm of left edge (reserved for I/O ring)
Every standard cell and macro needs a reliable VDD/VSS connection. The power grid is a hierarchical mesh of metal stripes that delivers current from the chip's I/O pads to every cell. Poor power grids cause IR drop — voltage loss across metal resistance — which reduces effective VDD at far-from-pad cells, causing timing failures and functional errors.
| Layer | Structure | Purpose |
|---|---|---|
| Top metal (M8–M10) | Power rings around core | Collect current from pads, distribute to stripes |
| Mid metals (M4–M7) | Wide horizontal + vertical stripes (mesh) | Low-resistance current distribution across die |
| Lower metals (M1–M3) | Standard cell rails (VDD/VSS rails in rows) | Last-mile delivery to every cell |
| Via stacks | M1↔M2↔...↔M10 via arrays | Connect all levels of the mesh |
IR drop = I × R, where I is the current demand of a region and R is the resistance of the metal path from pad to that region. Targets: static IR drop < 3% VDD, dynamic IR drop < 5% VDD. Violations require adding more power stripes or wider stripes.
# Create power rings around the core create_power_plan \ -nets {VDD VSS} \ -ring_width 8.0 \ -ring_spacing 2.0 \ -corner_bridge # Add power stripes on upper metals add_stripes \ -nets {VDD VSS} \ -layer M8 \ -direction horizontal \ -width 4.0 \ -spacing 2.0 \ -set_to_set_distance 40 add_stripes \ -nets {VDD VSS} \ -layer M7 \ -direction vertical \ -width 4.0 \ -spacing 2.0 \ -set_to_set_distance 40 # Connect standard cell rails to the grid sroute -connect {core_pin} -nets {VDD VSS} # Run IR drop analysis analyze_power_plan -nets {VDD VSS} -voltage 0.9
I/O pads are the interface between the chip core and the outside world — wire bonds or flip-chip bumps connect pads to the package. Each pad is a large cell (~50–100 µm wide) that contains ESD protection, level shifters, and drive-strength buffers.
The I/O ring surrounds the core area. Key pad types:
# Place I/O pads using an I/O constraints file place_io \ -io_guide_file io_constraints.tcl \ -flip_io_side auto # Manual pad placement (side: top/bottom/left/right, offset in µm) set_io_pin_constraint \ -pin_name clk \ -side left \ -offset 300 set_io_pin_constraint \ -pin_names {data_in[*]} \ -side bottom \ -range {100 900} # Insert pad fillers to complete the ring insert_pad_fillers -cell {PFILL10 PFILL5 PFILL1}
Pin assignment determines where each signal exits the chip boundary and connects to a wire bond or bump. Good pin assignment minimizes wire length between the chip pin and the first internal flip-flop that uses it, reducing routing congestion and improving signal integrity.
Floorplanning decisions made in hour one of physical design can cause failures that show up weeks later during routing or timing closure. Understanding the cascade helps explain why experienced PD engineers spend significant time at this stage.
A macro placed in the center of the die splits the routing channel in two. Thousands of nets that previously had a direct path now must detour around the macro. Congestion hotspots appear in placement, causing the router to use longer, noisier wires or to fail entirely with open nets.
High utilization forces the placer to pack cells tightly. Tight packing increases wire length (cells cannot be placed close to their fanouts), which increases net delay. A 10% increase in utilization can translate to 50–100 ps of additional net delay on critical paths — enough to miss timing.
Insufficient power stripes mean high resistance from pad to distant cells. Under high switching activity, IR drop can exceed 50 mV — reducing effective VDD by 5–10%. This slows down cells (delay is proportional to 1/VDD), causing setup violations at silicon that were not predicted in signoff because the power grid analysis was skipped or incorrectly modeled.
A clock pin placed on the opposite side of the die from the clock tree root requires a long clock wire with high insertion delay. This delay reduces the effective clock period available for functional logic. Similarly, data pins placed far from their first-stage FFs add routing delay that STA counts as part of the input timing budget.