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📐 Free Deep-Dive Series

RTL to Silicon

The complete ASIC design flow — from writing your first RTL to handing off GDS for fabrication. 10 chapters, deep theory, interactive demos at every step.

10
Chapters
10
Interactive Demos
~5h
Total Reading
Free
Always
Start Chapter 1 →
RTL CodingCh. 1 → SynthesisCh. 2 → FloorplanCh. 3 → PlacementCh. 4 → CTSCh. 5 → RoutingCh. 6 → STACh. 7 → DFTCh. 8 → PowerCh. 9 → TapeoutCh. 10
10 Chapters — The Full Flow
Each chapter covers one stage of the ASIC flow with in-depth theory and a hands-on interactive demo.
Chapter 01
RTL Coding
Write synthesizable Verilog — combinational logic, sequential design, FSMs, coding guidelines, and common RTL pitfalls that cause synthesis failures.
VerilogFSMSequentialLint
~30 min read⚡ FSM Visualizer→
Chapter 02
Logic Synthesis
How a synthesizer maps RTL to standard cells — technology mapping, timing constraints (SDC), area/power/timing trade-offs, and reading synthesis reports.
SDCNetlistTimingGenus/DC
~35 min read⚡ RTL→Gate Mapper→
Chapter 03
Floorplanning
Die size estimation, macro placement strategy, power grid planning, I/O ring, and how floorplan decisions cascade into timing, congestion and power.
Macro PlacementPower GridI/O Ring
~30 min read⚡ Floorplan Builder→
Chapter 04
Placement
Standard cell placement — legalization, timing-driven placement, congestion vs. timing trade-off, placement optimization, and scan-chain reordering.
LegalizationCongestionTiming-Driven
~28 min read⚡ Placement Visualizer→
Chapter 05
Clock Tree Synthesis
Building a balanced clock tree — skew targets, insertion delay, H-tree vs. fishbone topologies, useful skew, and post-CTS hold fixing.
SkewH-TreeBuffersHold Fix
~30 min read⚡ Clock Tree Builder→
Chapter 06
Routing
Global and detailed routing — track assignment, via optimization, DRC fixes, antenna violations, signal integrity (crosstalk, shielding), and ECO flows.
Global RouteDRCAntennaSI
~30 min read⚡ Routing Grid Demo→
Chapter 07
Static Timing Analysis
Setup and hold analysis, clock domain crossings, OCV/AOCV/POCV, multi-corner multi-mode signoff, ECO timing closure techniques.
Setup/HoldMCMMOCVSlack
~40 min read⚡ Timing Path Analyzer→
Chapter 08
Design for Test (DFT)
Scan insertion, ATPG, stuck-at and transition fault models, BIST (LBIST/MBIST), boundary scan (JTAG), fault coverage targets, and DFT sign-off.
ScanATPGBISTJTAG
~35 min read⚡ Scan Chain Visualizer→
Chapter 09
Power Analysis & Signoff
Dynamic and static power, IR drop and EM signoff, power domains and UPF, clock/power gating implementation, and power-aware physical design.
IR DropEMUPFDVFS
~35 min read⚡ IR Drop Heatmap→
Chapter 10
Tapeout
Final signoff — DRC/LVS/ERC, GDS merge, fill insertion, seal ring, chip assembly, mask generation, and what happens between GDS handoff and first silicon.
DRC/LVSGDSFillFirst Silicon
~30 min read⚡ Signoff Checklist→
Why this series is different
Most VLSI tutorials stop at theory. This series gives you working interactive demos at every stage.
🔬
Interactive at Every Step
Each chapter has a live demo — FSM visualizer, placement grid, timing path calculator, IR drop heatmap — not just diagrams.
🎯
Interview-Ready
Covers exactly what Google, Qualcomm, Apple, Samsung, and NVIDIA ask in physical design and RTL interviews.
⚡
Full Flow — No Gaps
From the first line of Verilog to GDS handoff — every stage explained with the same depth. No hand-waving.
🆓
Completely Free
No login, no paywall, no ads that block content. EcrioniX believes quality VLSI education should be accessible to everyone.