CDC Convergence & Divergence
— The Sneakiest Clock Domain Bugs

// CORRECT: Synchronize en_a → CLK_B first (hub).
// Fan en_b to Module B directly.
// Re-synchronize en_b → CLK_C for Module C.
// Both now agree: they see the SAME source value.

module top (
  input  clk_a, clk_b, clk_c, rst_n,
  input  en_a,
  output out_b, out_c
);

  // Stage 1: Sync en_a → CLK_B (single synchronizer, single resolution)
  reg [1:0] sync_to_b;
  always @(posedge clk_b or negedge rst_n)
    if (!rst_n) sync_to_b <= 2'b00;
    else        sync_to_b <= {sync_to_b[0], en_a};

  wire en_b = sync_to_b[1]; // Now stable in CLK_B domain

  // Stage 2a: Module B uses en_b directly — same clock domain
  assign out_b = en_b;

  // Stage 2b: Re-sync en_b → CLK_C. Source is now a stable CLK_B signal.
  // No metastability risk: en_b changed in CLK_B, not CLK_C, but it is
  // a stable level by the time it enters this second synchronizer.
  reg [1:0] sync_to_c;
  always @(posedge clk_c or negedge rst_n)
    if (!rst_n) sync_to_c <= 2'b00;
    else        sync_to_c <= {sync_to_c[0], en_b};

  assign out_c = sync_to_c[1];

endmodule

// CORRECT: Only req crosses the boundary via a 2-FF synchronizer.
// data_a is sampled in the CLK_B domain the cycle AFTER req_b goes high.
// By then, data_a has been stable for many CLK_B periods — it is safe to latch.
//
// Rule: source must hold data_a stable until the CLK_B ack is received.

module cdc_conv_fix (
  input        clk_a, clk_b, rst_n,
  input        req_a,
  input  [7:0] data_a,     // held stable in CLK_A until ack
  output       ack_b,      // pulsed back when data latched
  output [7:0] data_captured
);

  // Step 1: Synchronize req_a into CLK_B (single source of truth)
  reg [1:0] req_sync;
  always @(posedge clk_b or negedge rst_n)
    if (!rst_n) req_sync <= 2'b00;
    else        req_sync <= {req_sync[0], req_a};

  wire req_b      = req_sync[1];
  wire req_b_prev = req_sync[0]; // detect rising edge
  wire req_rise   = req_b & ~req_b_prev;

  // Step 2: Sample data_a only on the rising edge of req_b.
  //   At this point, req has been synchronized (≥2 CLK_B cycles old).
  //   data_a has been stable in CLK_A for at least those same cycles.
  //   Crossing a stable level never causes metastability.
  reg [7:0] data_latch;
  always @(posedge clk_b or negedge rst_n)
    if (!rst_n)      data_latch <= 8'h00;
    else if (req_rise) data_latch <= data_a; // safe: data_a is stable

  assign data_captured = data_latch;
  assign ack_b         = req_rise;   // pulse ack back to source

endmodule

// Full REQ/ACK handshake:
//  1. Source sets req_a=1, holds data_a stable.
//  2. req_a → 2-FF sync → req_b in CLK_B.
//  3. CLK_B captures data_a, asserts ack_b.
//  4. ack_b → 2-FF sync → ack_a in CLK_A.
//  5. CLK_A de-asserts req_a, may update data_a.

module req_ack_handshake (
  input        clk_a, clk_b, rst_n,
  // Source side
  input        send_a,       // pulse: source wants to send
  input  [7:0] data_a,
  output       ready_a,      // source can send next word
  // Destination side
  output       valid_b,
  output [7:0] data_b
);

  // ── Source FSM ──
  reg       req_a, ack_a;
  reg [7:0] data_hold;

  always @(posedge clk_a or negedge rst_n) begin
    if (!rst_n) begin req_a <= 0; data_hold <= 0; end
    else if (send_a && !req_a) begin
      req_a     <= 1;
      data_hold <= data_a;     // latch and hold until ack
    end else if (ack_a) begin
      req_a <= 0;
    end
  end
  assign ready_a = !req_a;

  // ── REQ sync: CLK_A → CLK_B ──
  reg [1:0] req_s;
  always @(posedge clk_b or negedge rst_n)
    if (!rst_n) req_s <= 0;
    else        req_s <= {req_s[0], req_a};

  wire req_b = req_s[1];

  // ── Destination: latch data on req_b rising edge ──
  reg [7:0] data_cap;
  reg       req_b_r, ack_b;
  always @(posedge clk_b or negedge rst_n) begin
    if (!rst_n) begin req_b_r <= 0; ack_b <= 0; data_cap <= 0; end
    else begin
      req_b_r <= req_b;
      if (req_b && !req_b_r) begin   // rising edge of req_b
        data_cap <= data_hold;        // safe: held stable in CLK_A
        ack_b    <= 1;
      end else
        ack_b <= 0;
    end
  end
  assign valid_b = (req_b && !req_b_r);
  assign data_b  = data_cap;

  // ── ACK sync: CLK_B → CLK_A ──
  reg [1:0] ack_s;
  always @(posedge clk_a or negedge rst_n)
    if (!rst_n) ack_s <= 0;
    else        ack_s <= {ack_s[0], ack_b};

  always @(posedge clk_a) ack_a <= ack_s[1];

endmodule