CDC Pulse Problem: Your Pulse Got Lost. Here's Why — and How to Fix It.

module toggle_sync (
    input  wire clk_src,
    input  wire clk_dst,
    input  wire rst_n,        // async active-low reset (or use separate resets)
    input  wire pulse_src,    // 1-cycle pulse in clk_src domain
    output wire pulse_dst     // 1-cycle pulse in clk_dst domain
);

    // ── Source domain: toggle FF ────────────────────────────────────
    reg toggle_s;
    always @(posedge clk_src or negedge rst_n)
        if (!rst_n) toggle_s <= 1'b0;
        else if (pulse_src) toggle_s <= ~toggle_s;

    // ── Destination domain: 3-stage sync + edge detect ─────────────
    // 3 stages: FF1 + FF2 for metastability, FF3 for edge detection
    (* ASYNC_REG = "TRUE" *)
    reg [2:0] sync_d;
    always @(posedge clk_dst or negedge rst_n)
        if (!rst_n) sync_d <= 3'b000;
        else        sync_d <= {sync_d[1:0], toggle_s};

    // Edge detect: XOR of stages 2 and 3 = 1 for exactly one cycle
    assign pulse_dst = sync_d[2] ^ sync_d[1];

endmodule

module pulse_stretch #(
    parameter STRETCH = 8     // extend to N source clock cycles
)(
    input  wire clk_src,
    input  wire rst_n,
    input  wire pulse_in,     // original 1-cycle pulse
    output wire stretched     // stretched level (feed into 2-FF sync)
);
    localparam W = $clog2(STRETCH + 1);
    reg [W-1:0] cnt;

    always @(posedge clk_src or negedge rst_n)
        if      (!rst_n)    cnt <= '0;
        else if (pulse_in)  cnt <= STRETCH[W-1:0]; // reload on new pulse
        else if (|cnt)      cnt <= cnt - 1'b1;

    assign stretched = |cnt;

endmodule

// ── Usage: stretched output → standard 2-FF sync → edge detect ─────
// sync_2ff u_sync (.clk_dst(clk_dst), .rst_n(rst_n),
//                  .async_in(stretched), .sync_out(sync_level));
//
// reg sync_prev;
// always @(posedge clk_dst or negedge rst_n)
//     if (!rst_n) sync_prev <= 0;
//     else        sync_prev <= sync_level;
// assign pulse_dst = sync_level && !sync_prev;  // rising edge detect

// ── SOURCE DOMAIN ──────────────────────────────────────────────────
module req_ack_src #(parameter DW = 8) (
    input  wire          clk_src, rst_n,
    input  wire          send,        // 1-cycle trigger from local logic
    input  wire [DW-1:0] data_in,
    output reg           req,
    output reg  [DW-1:0] tx_data,
    input  wire          ack_sync     // ACK synchronized back from destination
);
    always @(posedge clk_src or negedge rst_n) begin
        if (!rst_n) begin req <= 1'b0; tx_data <= '0; end
        else if (send && !req && !ack_sync) begin  // idle: accept new transfer
            tx_data <= data_in;
            req     <= 1'b1;
        end else if (ack_sync && req) begin          // ACK received: release
            req <= 1'b0;
        end
    end
endmodule

// ── DESTINATION DOMAIN ─────────────────────────────────────────────
module req_ack_dst #(parameter DW = 8) (
    input  wire          clk_dst, rst_n,
    input  wire          req_sync,    // REQ synchronized from source
    input  wire [DW-1:0] tx_data,     // stable data from source domain
    output reg           ack,
    output reg  [DW-1:0] rx_data
);
    reg req_prev;
    wire req_rise = req_sync && !req_prev;  // rising edge of synced REQ

    always @(posedge clk_dst or negedge rst_n) begin
        if (!rst_n) begin ack <= 1'b0; req_prev <= 1'b0; rx_data <= '0; end
        else begin
            req_prev <= req_sync;
            if (req_rise) begin     // new transfer detected
                rx_data <= tx_data;
                ack     <= 1'b1;
            end else if (!req_sync) begin  // REQ deasserted: release ACK
                ack <= 1'b0;
            end
        end
    end
endmodule

// ── TOP LEVEL: wire the two domains together with 2-FF syncs ───────
// sync_2ff u_req_sync (.clk_dst(clk_dst), .async_in(req), .sync_out(req_sync));
// sync_2ff u_ack_sync (.clk_dst(clk_src), .async_in(ack), .sync_out(ack_sync));