SystemVerilog
for RTL Design

Why SystemVerilog over Verilog?

Verilog (IEEE 1364) was designed in the 1980s for simulation. Its wire/reg ambiguity, manual sensitivity lists, and absence of type safety cause entire classes of RTL bugs that only surface at synthesis or in silicon. SystemVerilog (IEEE 1800) is a strict superset that fixes these issues without breaking any existing Verilog code.

The logic Type

In Verilog, wire is a net (driven continuously, required for port connections) and reg is a variable (driven from an always block). This distinction causes confusing errors. SystemVerilog introduces logic — a 4-state variable (0, 1, X, Z) that works in both contexts.

// Verilog — two separate types, easy to confuse
wire  [7:0] w_data;          // net — must be driven by assign or output
reg   [7:0] r_count;         // variable — driven from always block

// SystemVerilog — single type for everything
logic [7:0] data;            // works as wire (assign) or reg (always)
logic [7:0] count;           // context determines wire vs flip-flop
logic       valid, ready;    // single-bit signalsSystemVerilog

Intent-Explicit Procedural Blocks

Verilog's always @(...) is ambiguous — the same syntax describes flip-flops, latches, and combinational logic. SystemVerilog adds three dedicated keywords that document intent and enable semantic checking by the simulator and synthesis tool.

// ─── always_ff : D flip-flop with async reset ───
always_ff @(posedge clk or negedge rst_n) begin
  if (!rst_n)
    count <= 8'b0;
  else
    count <= count + 1'b1;
end

// ─── always_comb : combinational decoder ───
always_comb begin
  // No sensitivity list needed — tool infers it automatically
  case (opcode)
    2'b00: result = a + b;
    2'b01: result = a - b;
    2'b10: result = a & b;
    default: result = 8'b0;
  endcase
end

// ─── always_latch : level-sensitive enable latch ───
always_latch begin
  if (en)
    q = d;          // blocking assignment — latch transparent when en=1
endSystemVerilog

Enumerated Types for FSM Design

Defining FSM states as integer literals is error-prone and produces unreadable waveforms. SystemVerilog typedef enum gives states symbolic names, enables compile-time checks for illegal state assignments, and makes waveform debugging trivial — the debugger shows state names, not bit patterns.

// Define state encoding type — tool respects the bit-width
typedef enum logic [1:0] {
  IDLE  = 2'b00,
  FETCH = 2'b01,
  EXEC  = 2'b10,
  DONE  = 2'b11
} state_t;

module fetch_ctrl (
  input  logic   clk, rst_n, start,
  output logic   done
);
  state_t state, next_state;

  // Sequential state register
  always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) state <= IDLE;
    else        state <= next_state;
  end

  // Combinational next-state + output logic
  always_comb begin
    next_state = state;   // default: hold state
    done       = 1'b0;
    unique case (state)
      IDLE:  if (start) next_state = FETCH;
      FETCH: next_state = EXEC;
      EXEC:  next_state = DONE;
      DONE:  begin done = 1'b1; next_state = IDLE; end
    endcase
  end
endmoduleSystemVerilog

The unique case keyword tells the synthesis tool that exactly one branch matches — enabling parallel decode optimization. Assigning an out-of-range value like state = 3'b100 is a compile-time error because the enum only holds 2-bit values.

Packed Structs and Arrays

SystemVerilog structs let you group related signals into a named type. Packed structs are stored as a contiguous bit vector — fully synthesizable, sliceable, and usable in arithmetic. This replaces error-prone manual bit-field extraction and makes bus definitions self-documenting.

// Define a packed AXI-like data struct
typedef struct packed {
  logic [31:0] data;
  logic [3:0]  strb;    // byte write strobes
  logic        valid;
  logic        last;
} axi_data_t;             // total: 38 bits, contiguous

module packet_filter (
  input  axi_data_t  rx,
  output axi_data_t  tx
);
  // Access fields by name — no manual bit slicing
  always_comb begin
    tx       = rx;              // copy entire struct
    tx.valid = rx.valid & rx.strb[0];  // byte 0 must be valid
    tx.data  = rx.data & 32'hFFFF_00FF;
  end
endmodule

// Packed arrays — contiguous bit vectors
logic [3:0][7:0] word;    // 4 bytes packed = 32 bits
assign word[2] = 8'hAB;  // access byte 2 by index
assign out = word[31:16]; // can still slice as a flat vector

// Unpacked arrays — memory-like, one element per address
logic [7:0] mem [0:255];   // 256-byte RAM arraySystemVerilog

Interfaces and Modports

An interface bundles a group of related signals into a single named object. Modports define directional views of the interface — master vs slave, or initiator vs target — enforced at the port boundary. This eliminates the copy-paste port lists that cause connection bugs in large designs.

// Define the interface
interface simple_bus #(parameter W = 8) (
  input logic clk
);
  logic [W-1:0] data;
  logic         valid;
  logic         ready;

  // Modport directions — master drives data/valid, reads ready
  modport master (output data, valid, input ready, input clk);
  modport slave  (input  data, valid, output ready, input clk);
endinterface

// Producer module uses master modport
module producer (simple_bus.master bus);
  always_ff @(posedge bus.clk) begin
    bus.valid <= 1'b1;
    bus.data  <= bus.data + 1'b1;
  end
endmodule

// Consumer module uses slave modport
module consumer (simple_bus.slave bus);
  always_comb
    bus.ready = 1'b1;  // always accept
endmodule

// Top-level instantiation — one port per module
module top (input logic clk);
  simple_bus #(.W(16)) bus (.clk(clk));  // interface instance
  producer p (.bus(bus));
  consumer c (.bus(bus));
endmoduleSystemVerilog

Modport direction violations are caught by the tool at elaboration — if the consumer accidentally drives bus.data, it is an error. Without interfaces, this would be a silent multi-driver bug discovered only in simulation.

unique and priority Case Statements

Plain case in Verilog requires synthesis pragmas (// synthesis parallel_case) to get efficient decode logic. SystemVerilog adds unique case and priority case as first-class keywords that achieve the same result with formal simulation semantics.

// unique case — tool generates optimal parallel decode
always_comb begin
  unique case (sel)          // exactly one branch matches
    2'b00: out = a;
    2'b01: out = b;
    2'b10: out = c;
    2'b11: out = d;
  endcase
end

// priority case — first matching branch wins (like casex)
always_comb begin
  priority case (1'b1)        // equivalent to priority encoder
    irq[3]: grant = 3;
    irq[2]: grant = 2;
    irq[1]: grant = 1;
    irq[0]: grant = 0;
  endcase
endSystemVerilog

Parameters, Localparams & Typedefs

SystemVerilog adds typed parameters and a richer type system for constants. Typed parameters catch dimension mismatches at elaboration time — passing a string where an integer is expected becomes an error rather than a silent truncation.

// Verilog — untyped, width can mismatch silently
parameter DEPTH = 16;
parameter WIDTH = 8;

// SystemVerilog — typed parameters (preferred)
parameter int unsigned DEPTH = 16;   // integer type enforced
parameter int unsigned WIDTH = 8;
localparam int unsigned ADDR_W = $clog2(DEPTH); // derived, not overridable

// Typedef for reusable types across modules
typedef logic [WIDTH-1:0]      data_t;
typedef logic [ADDR_W-1:0]     addr_t;

module fifo #(
  parameter int unsigned DEPTH = 16,
  parameter int unsigned WIDTH = 8
) (
  input  logic  clk, rst_n,
  input  logic  wr_en, rd_en,
  input  logic [WIDTH-1:0]          din,
  output logic [WIDTH-1:0]          dout,
  output logic                        full, empty
);
  localparam int unsigned AW = $clog2(DEPTH);
  logic [WIDTH-1:0] mem [0:DEPTH-1];
  logic [AW:0]       wr_ptr, rd_ptr;   // extra bit for full/empty distinction

  assign full  = (wr_ptr == {~rd_ptr[AW], rd_ptr[AW-1:0]});
  assign empty = (wr_ptr == rd_ptr);

  always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      wr_ptr <= '0; rd_ptr <= '0;
    end else begin
      if (wr_en && !full)  begin mem[wr_ptr[AW-1:0]] <= din;  wr_ptr <= wr_ptr + 1'b1; end
      if (rd_en && !empty) begin dout <= mem[rd_ptr[AW-1:0]]; rd_ptr <= rd_ptr + 1'b1; end
    end
  end
endmoduleSystemVerilog

Synthesis Pitfalls & What to Avoid

SystemVerilog has two worlds: the RTL/synthesizable subset used in design, and the verification subset (OOP, dynamic memory, randomization) used in testbenches. Never mix them in a synthesizable module.

Frequently Asked Questions