Serial Peripheral Interface
SPI · CPOL/CPHA · Verilog Master

// ─────────────────────────────────────────────────────
//  SPI Master — parameterized, all 4 modes, CLK_DIV
//  sclk_freq = clk / (2 * CLK_DIV)
// ─────────────────────────────────────────────────────
module spi_master #(
  parameter CLK_DIV = 4,   // sclk = clk / (2*CLK_DIV)
  parameter CPOL    = 0,   // 0: idle low,  1: idle high
  parameter CPHA    = 0    // 0: sample leading, 1: sample trailing
)(
  input             clk, rst_n,
  input             start,
  input  [7:0]      tx_data,
  output reg [7:0] rx_data,
  output reg        done,
  // SPI pins
  output reg        sclk,
  output reg        mosi,
  input             miso,
  output reg        cs_n
);

  // FSM states
  localparam IDLE      = 2'd0,
             ASSERT_CS = 2'd1,
             TRANSFER  = 2'd2,
             DONE      = 2'd3;

  reg [1:0]  state;
  reg [7:0]  tx_shift, rx_shift;
  reg [3:0]  bit_cnt;    // counts 0..15 (rising+falling per bit)
  reg [$clog2(CLK_DIV)-1:0] div_cnt;
  reg         clk_en;    // sclk toggle strobe
  reg         sclk_r;    // internal sclk state

  // ── Clock divider ────────────────────────────────
  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      div_cnt <= 0;
      clk_en  <= 1'b0;
    end else begin
      if (div_cnt == CLK_DIV[0+:$clog2(CLK_DIV)]-1) begin
        div_cnt <= 0;
        clk_en  <= 1'b1;
      end else begin
        div_cnt <= div_cnt + 1;
        clk_en  <= 1'b0;
      end
    end
  end

  // ── Main FSM ─────────────────────────────────────
  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      state    <= IDLE;
      cs_n     <= 1'b1;
      sclk_r   <= CPOL[0];    // idle state
      sclk     <= CPOL[0];
      mosi     <= 1'b0;
      done     <= 1'b0;
      bit_cnt  <= 0;
      tx_shift <= 0;
      rx_shift <= 0;
      rx_data  <= 0;
    end else begin
      done <= 1'b0;  // pulse for one cycle only

      case (state)

        // ── IDLE: wait for start pulse ──────────────
        IDLE: begin
          cs_n   <= 1'b1;
          sclk_r <= CPOL[0];
          sclk   <= CPOL[0];
          if (start) begin
            tx_shift <= tx_data;
            bit_cnt  <= 0;
            state    <= ASSERT_CS;
          end
        end

        // ── ASSERT_CS: pull CS low, wait one div ───
        ASSERT_CS: begin
          cs_n <= 1'b0;
          // For CPHA=0, put MSB on MOSI now (before first edge)
          if (CPHA == 0)
            mosi <= tx_shift[7];
          if (clk_en)
            state <= TRANSFER;
        end

        // ── TRANSFER: 8 bits, 16 half-cycles ───────
        TRANSFER: begin
          if (clk_en) begin
            sclk_r <= ~sclk_r;
            sclk   <= ~sclk_r;  // one cycle delay (pipeline)

            if (CPHA == 0) begin
              // Sample on leading edge, shift on trailing
              if (sclk_r == CPOL[0]) begin   // leading edge
                rx_shift <= {rx_shift[6:0], miso};
                bit_cnt  <= bit_cnt + 1;
              end else begin                    // trailing edge
                mosi <= tx_shift[7 - (bit_cnt[2:0])];
              end
            end else begin
              // CPHA=1: shift on leading edge, sample on trailing
              if (sclk_r == CPOL[0]) begin   // leading edge — shift
                mosi <= tx_shift[7 - bit_cnt[2:0]];
              end else begin                    // trailing edge — sample
                rx_shift <= {rx_shift[6:0], miso};
                bit_cnt  <= bit_cnt + 1;
              end
            end

            if (bit_cnt == 8)
              state <= DONE;
          end
        end

        // ── DONE: deassert CS, capture rx_data ─────
        DONE: begin
          cs_n    <= 1'b1;
          rx_data <= rx_shift;
          done    <= 1'b1;
          sclk_r  <= CPOL[0];
          sclk    <= CPOL[0];
          mosi    <= 1'b0;
          state   <= IDLE;
        end

        default: state <= IDLE;
      endcase
    end
  end

endmodule

// ─────────────────────────────────────────────────────
//  SPI Slave — Mode 0 (CPOL=0, CPHA=0)
//  Samples MOSI on rising SCLK, drives MISO MSB-first
// ─────────────────────────────────────────────────────
module spi_slave (
  input             clk,       // system clock (for output staging)
  input             rst_n,
  // SPI pins
  input             sclk,
  input             mosi,
  output reg        miso,
  input             cs_n,
  // Application interface
  input  [7:0]      tx_data,   // byte to send back to master
  output reg [7:0] rx_data,   // byte received from master
  output reg        rx_valid   // pulses high for one sys clk after full byte
);

  reg [7:0] rx_shift, tx_shift;
  reg [2:0] bit_cnt;

  // ── Edge detection on SPI clock ─────────────────
  reg sclk_d;
  wire sclk_rising  = (!sclk_d) && sclk;
  wire sclk_falling =  sclk_d  && (!sclk);

  always @(posedge clk or negedge rst_n)
    if (!rst_n) sclk_d <= 1'b0;
    else        sclk_d <= sclk;

  // ── Load TX shift register when CS asserted ──────
  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      tx_shift <= 8'h00;
      rx_shift <= 8'h00;
      rx_data  <= 8'h00;
      rx_valid <= 1'b0;
      bit_cnt  <= 3'd7;  // MSB first
      miso     <= 1'b0;
    end else begin
      rx_valid <= 1'b0;

      if (cs_n) begin
        // CS deasserted: reset counters, pre-load TX
        bit_cnt  <= 3'd7;
        tx_shift <= tx_data;
        miso     <= 1'b0;  // tristate (driven low when idle)
      end else begin
        // Rising SCLK: sample MOSI (Mode 0)
        if (sclk_rising) begin
          rx_shift <= {rx_shift[6:0], mosi};
          if (bit_cnt == 3'd0) begin
            rx_data  <= {rx_shift[6:0], mosi};  // latch full byte
            rx_valid <= 1'b1;
          end
        end
        // Falling SCLK: shift out MISO (Mode 0)
        if (sclk_falling) begin
          miso    <= tx_shift[bit_cnt];
          if (bit_cnt != 3'd0)
            bit_cnt <= bit_cnt - 1;
          else
            bit_cnt <= 3'd7;  // wrap for continuous transfer
        end
      end
    end
  end

endmodule