I²C Protocol
Open-Drain Bus · 7-Bit Addressing · ACK/NACK

1. What is I²C?

2. SDA, SCL & the Open-Drain Bus

Why open-drain?

Pull-up resistor sizing

3. Bus Transactions — START, Data, ACK, STOP

START condition

Address + R/W byte

ACK / NACK

Data bytes

STOP condition

4. 7-bit Addressing

5. Clock Stretching

6. Multi-Master & Arbitration

7. Verilog I²C Master

A synthesizable I²C master FSM. Supports write transactions (START → addr+W → ACK → data → ACK → STOP). The SDA output uses a tristate-style output-enable to implement open-drain in RTL.

module i2c_master #(
  parameter CLK_DIV = 125  // 100 kHz SCL from 25 MHz system clk (25M/125/2 = 100kHz)
)(
  input        clk, rst_n,
  input        start,       // pulse to begin transaction
  input  [6:0] addr,        // 7-bit device address
  input        rw,          // 0=write, 1=read
  input  [7:0] tx_data,     // byte to write
  output reg [7:0] rx_data, // byte read from slave
  output reg   done,        // transaction complete
  output reg   ack_err,     // slave sent NACK
  // open-drain I2C pins (use external pull-ups)
  inout        sda,
  output reg   scl
);

  // ── Clock divider ────────────────────────────────────────────
  reg [$clog2(CLK_DIV)-1:0] clk_cnt;
  reg clk_en;
  always @(posedge clk) begin
    if (!rst_n) begin clk_cnt <= 0; clk_en <= 0; end
    else if (clk_cnt == CLK_DIV-1) begin clk_cnt <= 0; clk_en <= 1; end
    else begin clk_cnt <= clk_cnt + 1; clk_en <= 0; end
  end

  // ── Open-drain SDA ───────────────────────────────────────────
  reg sda_oe, sda_out;
  assign sda = sda_oe ? (1'b0) : 1'bz;  // drive low or release (pull-up takes it high)

  // ── FSM states ───────────────────────────────────────────────
  localparam
    IDLE     = 4'd0, ST_START = 4'd1, ST_ADDR  = 4'd2,
    ST_ACK1  = 4'd3, ST_DATA  = 4'd4, ST_ACK2  = 4'd5,
    ST_STOP  = 4'd6, ST_DONE  = 4'd7;

  reg [3:0] state;
  reg [3:0] bit_cnt;
  reg [7:0] shift_reg;
  reg        scl_phase;   // 0=low half, 1=high half

  always @(posedge clk) begin
    if (!rst_n) begin
      state <= IDLE; scl <= 1; sda_oe <= 0;
      done <= 0; ack_err <= 0; scl_phase <= 0;
    end else if (clk_en) begin
      done <= 0;
      case (state)

        IDLE: begin
          scl <= 1; sda_oe <= 0;  // bus idle (both lines released HIGH)
          if (start) begin
            shift_reg <= {addr, rw};
            bit_cnt   <= 7;
            state     <= ST_START;
          end
        end

        ST_START: begin
          // SDA falls while SCL high → START condition
          sda_oe <= 1;  // pull SDA low
          scl    <= 1;
          state  <= ST_ADDR;
          scl_phase <= 0;
        end

        ST_ADDR: begin
          if (!scl_phase) begin
            scl <= 0;
            sda_oe <= !shift_reg[7];  // drive 0: pull low; drive 1: release
            scl_phase <= 1;
          end else begin
            scl <= 1;
            scl_phase <= 0;
            if (bit_cnt == 0) state <= ST_ACK1;
            else begin shift_reg <= {shift_reg[6:0], 1'b0}; bit_cnt <= bit_cnt - 1; end
          end
        end

        ST_ACK1: begin
          if (!scl_phase) begin
            scl <= 0; sda_oe <= 0;  // release SDA — slave drives ACK
            scl_phase <= 1;
          end else begin
            scl <= 1;
            ack_err   <= sda;   // if SDA=1 → NACK
            shift_reg <= tx_data;
            bit_cnt   <= 7;
            scl_phase <= 0;
            state     <= ST_DATA;
          end
        end

        ST_DATA: begin
          if (!scl_phase) begin
            scl    <= 0;
            sda_oe <= !shift_reg[7];
            scl_phase <= 1;
          end else begin
            scl <= 1;
            scl_phase <= 0;
            if (bit_cnt == 0) state <= ST_ACK2;
            else begin shift_reg <= {shift_reg[6:0], 1'b0}; bit_cnt <= bit_cnt - 1; end
          end
        end

        ST_ACK2: begin
          if (!scl_phase) begin
            scl <= 0; sda_oe <= 0;
            scl_phase <= 1;
          end else begin
            scl <= 1;
            ack_err <= ack_err | sda;
            scl_phase <= 0;
            state <= ST_STOP;
          end
        end

        ST_STOP: begin
          // SDA rises while SCL high → STOP condition
          if (!scl_phase) begin
            scl <= 0; sda_oe <= 1;  // pull SDA low first
            scl_phase <= 1;
          end else begin
            scl <= 1;
            sda_oe <= 0;   // release SDA → HIGH while SCL HIGH = STOP
            state <= ST_DONE;
          end
        end

        ST_DONE: begin done <= 1; state <= IDLE; end
      endcase
    end
  end
endmoduleCopy

8. Applications