10 questions that separate engineers who memorise formulas from those who truly understand timing. Each question has exactly one trap hidden in the wrong answers.
Static Timing Analysis (STA) is the formal verification method used to confirm that every data path in a chip meets its timing constraints before fabrication. Unlike dynamic simulation, STA checks all paths simultaneously without test vectors — making it the industry-standard sign-off method for every digital ASIC and FPGA design. This quiz targets the concepts that trip up experienced engineers in interviews and on real tapeouts: not the definitions, but the consequences — what happens to hold timing when you fix a setup violation, which PVT corner applies to the capture clock versus the launch path, and how CPPR removes an artifact that STA tools would otherwise double-count.
Setup slack = Required time − Arrival time. The required time is the capture clock edge minus the flip-flop's setup time. The arrival time is how long the data takes to travel from the launch flip-flop through combinational logic to the capture flip-flop's D input. Negative slack means the data arrives too late: the path fails timing and the chip will not work at the target frequency.
Clock skew — the difference in clock arrival times between launch and capture flip-flops — directly shifts the required time. When the capture clock arrives earlier than the launch clock (negative skew), the capture edge moves earlier, closing the setup window by exactly the skew amount. This is one of the most common traps in STA calculations: engineers who add the skew instead of subtracting it will predict false positive slack and miss a real silicon violation. On a 5 ns clock with 0.4 ns early capture skew and 0.3 ns setup time, the required time is (5.0 − 0.4) − 0.3 = 4.3 ns, not 5.0 − 0.3 = 4.7 ns.
Hold slack = Minimum data arrival − Capture edge arrival − Hold time. Hold is a same-launch-edge check: data that launches on cycle N must stay stable long enough for the capture flip-flop to sample it on the same clock edge. This makes hold independent of clock period — increasing the clock period does not help a hold violation at all.
Positive skew (capture clock arriving later) helps setup timing because data has more time to travel before the capture edge. But that same late capture edge extends the hold window — data must remain stable until a later edge. This is the fundamental seesaw: anything that loosens setup tightens hold. Fixing setup violations by adding delay to the capture clock path will worsen hold violations on that same path. The correct fix for a hold violation is adding delay buffers on the data path, which increases minimum data arrival time without affecting the clock edge timing.
Process, voltage, and temperature variation means manufactured chips have a range of delays across their specified operating conditions. STA uses worst-case corner combinations to guarantee correctness across the entire range. For setup sign-off, the data (launch) path uses a Slow-Slow corner — maximising data delay — while the capture clock path uses a Fast-Fast corner — minimising clock insertion delay and pulling the capture edge earlier. Applying Slow-Slow to both sides is a common mistake that produces an optimistically relaxed required time and can miss real setup failures in manufactured silicon. For hold sign-off, the corners reverse: Fast-Fast on the data path (data arrives as early as possible) and Slow-Slow on the capture clock path (capture edge arrives as late as possible).
On-Chip Variation (OCV) analysis applies separate derating multipliers to the launch and capture paths within the same timing check to model spatial variation on the die — cells in different locations may have different delays due to local process gradients, IR drop, or thermal gradients. For a setup check under OCV, the launch path is derated slow (maximum delay) and the capture clock path is derated fast (minimum delay), creating the most pessimistic setup scenario.
Common Path Pessimism Removal (CPPR) corrects a double-counting artifact that OCV introduces. The launch and capture clock paths share a common trunk from the PLL to the branch point where they diverge. OCV simultaneously derate this shared trunk as slow on the launch side and fast on the capture side — but the physical cells in the common trunk cannot actually be both slow and fast at the same time. CPPR adds back the removed pessimism from the shared segment, producing a more realistic slack result without hiding the real variation that exists on the unique post-branch segments.
Pre-CTS uncertainty covers unknown skew (200–300 ps). Post-CTS, actual skew is measured and uncertainty drops to skew + PLL jitter (~130–160 ps). Leaving pre-CTS values in post-CTS runs wastes timing margin and generates false violations that burn ECO cycles.
Use set_clock_groups -asynchronous for truly asynchronous domains — it removes all cross-domain setup and hold checks while preserving within-domain analysis. set_false_path works per-path but may miss derived clocks and doesn't scale across large designs.
Fix hold violations by adding delay buffers to the data path — this increases minimum data arrival without touching clock timing. Fix setup violations by reducing combinational logic depth, retiming, or adding pipeline stages. Confusing the fix direction makes timing worse.