Every chip that leaves the fab must be tested. But there are two fundamentally different philosophies of testing — one checks what was built, the other checks what it does. Understanding both is essential for any DFT or verification engineer.
| Property | Structural Testing | Functional Testing |
|---|---|---|
| Goal | Detect manufacturing defects | Verify design correctness & spec compliance |
| Fault model | Stuck-at, transition, path delay, bridging | Specification failures, protocol violations, data errors |
| Pattern source | ATPG tool (automatic) | Design spec, simulation, BIST engine |
| DFT required? | Yes — scan chains, test pins | Optional (BIST) or No (external functional ATE) |
| Test speed | Slow scan shift speed (not at-speed) | At-speed or functional speed |
| Test time | Milliseconds (high vector parallelism) | Seconds to minutes (full boot, SW execution) |
| What it misses | Functional bugs, spec violations | Low-level defects (sticky shorts, resistive bridges) |
| Used at | Wafer sort, package test (ATE floor) | Board bring-up, system integration, field diagnostics |
| Industry metric | Fault coverage % (99%+ target) | Functional test coverage vs. spec |
| Typical cost | $0.10–$5.00 per chip (ATE time) | Higher — board, SW, longer test time |
A fault model is a mathematical abstraction of what a physical manufacturing defect looks like at the logic level. The four primary fault models cover the vast majority of real silicon defects.
Structural tests need to control and observe every flip-flop in the design. In normal operation, most flip-flops are buried deep inside the chip — unreachable from the primary I/O pins. The scan chain solves this by converting all flip-flops into a giant shift register.
| Pin Added to Each FF | Function | Active When |
|---|---|---|
| Scan In (SI) | Serial data input for shifting test patterns into the flop | SE = 1 (scan mode) |
| Scan Enable (SE) | Mux select: 0 = functional path, 1 = scan path | Controlled by test controller |
| Scan Out (SO) | Serial output — connects to SI of the next flop in the chain | SE = 1 (shift phase) |
// Scan-enabled D flip-flop (SDFF)
// Synthesis inserts these automatically after DFT insertion
module scan_dff (
input logic clk,
input logic rst_n,
input logic d, // functional data input
input logic si, // scan serial input
input logic se, // scan enable: 1=scan mode, 0=functional
output logic q,
output logic so // scan serial output (= q, feeds next FF)
);
logic d_mux;
assign d_mux = se ? si : d; // mux: functional vs scan path
assign so = q; // scan output is FF output
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) q <= 1'b0;
else q <= d_mux;
end
endmodule
// In a design with N flip-flops, they are chained:
// scan_in → FF[0].si → FF[0].so → FF[1].si → ... → FF[N-1].so → scan_out
// Pattern shift-in: apply N clocks with SE=1
// Capture: apply 1 clock with SE=0 (functional capture)
// Shift-out: apply N clocks with SE=1, sample scan_out
| ATPG Tool | Vendor | Fault Models Supported |
|---|---|---|
| TetraMAX (TMAX) | Synopsys | Stuck-at, transition, path delay, IDDQ, cell-aware |
| Modus | Cadence | Stuck-at, transition, path delay, cell-aware, bridge |
| FastScan / Tessent | Siemens (Mentor) | Stuck-at, transition, path delay, IDDQ, cell-aware |
Functional tests verify that a chip behaves correctly under real operating conditions. Unlike structural tests that use artificial patterns, functional tests use real application vectors — or self-test engines that mimic real operation.
Every SoC contains multiple memories (SRAMs, ROMs, register files). Memories are particularly prone to manufacturing faults (stuck bits, coupling faults, address decoder faults). MBIST embeds a hardware FSM inside the chip that tests all memories autonomously — no ATE required.
| MBIST Algorithm | What It Tests | Pattern Written/Read |
|---|---|---|
| March C− | Stuck-at, transition, coupling faults (most common) | ↑W0, ↑R0W1, ↑R1W0, ↓R0W1, ↓R1W0, ↓R0 |
| Checkerboard | Adjacent-cell coupling (alternating 0/1 pattern) | 0101…/1010… written, read back, inverted, read again |
| Walking 1s / 0s | Address decoder faults, bit-line opens | Single 1 (or 0) walked through all addresses |
| GALPAT | All coupling faults (exhaustive but slow) | Each cell flipped, all others read — O(N²) complexity |
| March B | Unlinked memory faults | 9-operation march sequence covering all fault types |
// MBIST controller — March C- on a 256×8 SRAM
// 6 operations: ↑W0, ↑R0W1, ↑R1W0, ↓R0W1, ↓R1W0, ↓R0
module mbist_ctrl #(
parameter DEPTH = 256,
parameter WIDTH = 8
)(
input logic clk, rst_n, bist_start,
output logic bist_done, bist_pass,
// SRAM interface
output logic [7:0] mem_addr,
output logic [7:0] mem_wdata,
output logic mem_we,
input logic [7:0] mem_rdata
);
typedef enum logic [2:0] {
IDLE, OP0_W0, OP1_R0W1, OP2_R1W0,
OP3_R0W1_DN, OP4_R1W0_DN, OP5_R0, DONE
} state_t;
state_t state;
logic [7:0] addr;
logic fail_flag;
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
state <= IDLE; bist_done <= 0; bist_pass <= 0;
addr <= 0; fail_flag <= 0;
end else begin
mem_we <= 0;
case (state)
IDLE: if (bist_start) begin state <= OP0_W0; addr <= 0; end
OP0_W0: begin // ↑W0: write 0 to all addresses (ascending)
mem_we <= 1; mem_wdata <= 8'h00; mem_addr <= addr;
if (addr == DEPTH-1) begin state <= OP1_R0W1; addr <= 0; end
else addr <= addr + 1;
end
OP1_R0W1: begin // ↑R0W1: read 0, write 1 (ascending)
mem_addr <= addr;
if (mem_rdata != 8'h00) fail_flag <= 1; // read verify
mem_we <= 1; mem_wdata <= 8'hFF;
if (addr == DEPTH-1) begin state <= OP2_R1W0; addr <= 0; end
else addr <= addr + 1;
end
// ... remaining operations follow same pattern ...
DONE: begin bist_done <= 1; bist_pass <= ~fail_flag; end
endcase
end
end
endmodule
LBIST tests the chip's logic (not memories) by generating pseudo-random test patterns on-chip and compressing the outputs into a signature that is compared against a golden value.
| Component | Full Name | Function |
|---|---|---|
| PRPG | Pseudo-Random Pattern Generator | LFSR that generates pseudo-random patterns and feeds them into the scan chains as test stimuli |
| MISR | Multiple Input Shift Register | XOR-based compactor at the scan chain outputs — compresses millions of response bits into a 32-bit or 64-bit signature |
| Golden Signature | Expected MISR output | Pre-computed from a defect-free simulation — stored in ROM or OTP memory on-chip |
| LBIST Controller | FSM managing the test | Controls PRPG seed, number of patterns, capture mode, MISR read-out, and pass/fail comparison |
Boundary scan adds a shift register cell around every I/O pin of every chip on a PCB. By daisy-chaining these cells through the standard 4-pin JTAG interface (TCK, TMS, TDI, TDO), a test controller can drive signals onto the board and observe responses — without any physical probe access to internal nodes.
| JTAG Pin | Name | Function |
|---|---|---|
| TCK | Test Clock | Drives the boundary scan shift register — typically 1–100 MHz |
| TMS | Test Mode Select | Navigates the TAP (Test Access Port) state machine — 16 states |
| TDI | Test Data In | Serial input for shifting data/instructions into the scan register |
| TDO | Test Data Out | Serial output from the last cell in the chain — observed data |
| TRST* | Test Reset (optional) | Asynchronously resets the TAP state machine |
What boundary scan tests: Board-level interconnect — solder joints between chips, trace opens/shorts, chip-to-chip connectivity. Also used for in-system programming (flash loading), debugging (via ARM Debug Access Port extensions), and field diagnostics.
Functional ATE vectors apply real application patterns — boot sequences, instruction execution, DMA transfers, protocol handshakes — to the packaged chip on the ATE floor. These complement structural tests by catching specification failures that structural patterns cannot detect:
| Test Stage | Test Types Used | What's Caught | Cost/Chip |
|---|---|---|---|
| Wafer Sort (EWS) | Structural: stuck-at, transition, IDDQ | Gross manufacturing defects before packaging — saves packaging cost on bad die | Low (ms/chip) |
| Package Test (Final) | Structural: all faults + functional: MBIST, LBIST, boundary scan | Defects introduced during packaging, final quality gate | Medium ($0.10–$5) |
| System Bring-up | Functional: BIST, JTAG, board-level | Board assembly defects, chip-to-chip interface issues, firmware compatibility | High (hours/board) |
| Power-on (In-field) | Functional: LBIST (automotive), MBIST | Latent defects that develop over time (aging), confirms chip is healthy before safety-critical operation | Minimal (seconds) |
| Failure Analysis | All types + physical FA (FIB, SEM) | Root cause of field returns — feeds back to yield improvement | High (days/sample) |
Fault Coverage (FC) = (Detected Faults + Potentially Detected Faults) / Total Modelled Faults × 100%
| Fault Category | Symbol | Meaning |
|---|---|---|
| Detected | DT | At least one pattern activates and observes this fault — definitely tested |
| Potentially Detected | PD | Pattern activates the fault but the effect may be masked — possibly tested |
| Undetected | UD | No pattern found that detects this fault — either ATPG couldn't find one or the fault is redundant |
| Redundant | RE | Mathematically proven to be undetectable — the defect cannot change the observable output for any input. Excluded from coverage calculation. |
| Not Controlled / Not Observed | NC/NO | Fault cannot be detected because the node can't be set (NC) or the effect can't be observed (NO) — often X-state sources or black boxes |
These questions appear at Qualcomm, Intel, NVIDIA, Texas Instruments, Broadcom, MediaTek, and semiconductor test companies targeting DFT engineers and digital design engineers.
Structural testing targets manufacturing defects using abstract fault models (stuck-at, transition, bridging). Patterns are generated automatically by ATPG. It does not care what the chip is supposed to do — only whether physical wires and gates are intact. Metric: fault coverage %.
Functional testing verifies that the chip meets its specification by applying real application stimuli and checking outputs. It catches bugs in the design, not defects in manufacturing. Examples: MBIST (does this memory read back what was written?), functional ATE vectors (does the processor execute ADD correctly?).
Key interview point: A chip can pass 100% structural coverage and still be functionally broken if there's a design bug. A chip can also pass all functional tests but have a latent defect that causes early field failure — which structural testing would catch.
Without scan chains, internal flip-flops are only reachable through long chains of combinational logic from primary inputs. To set a specific flip-flop to a known state, you might need to apply hundreds of clock cycles of specific input patterns — and then you can only observe its effect after propagating through more logic to a primary output.
Scan chains make every flip-flop directly controllable (shift in any value) and directly observable (shift out its captured value) with only 2×N clock cycles regardless of design depth (N = chain length). This transforms an exponentially hard test problem into a linear one.
The area overhead is typically 5–10% for the added scan muxes, but the alternative — untestable or uneconomically testable silicon — is far worse.
Stuck-at fault (SAF): A wire is permanently fixed at 0 or 1 — it cannot change regardless of what logic drives it. Modelled as a DC defect (short to rail). Detected by applying the opposite value and checking if the output changes. Tests can run at slow speed — just need to set the stuck node to the opposite value.
Transition fault (TF): A wire CAN change, but does so too slowly. It fails to complete a 0→1 or 1→0 transition within the clock period. Modelled as a resistive open or weak drive. Requires at-speed testing (launch at functional frequency) because a slow-to-rise fault is invisible at reduced test frequency.
In practice, stuck-at tests are run first (they're cheaper — no speed constraints). Transition tests are added to catch timing-related manufacturing defects that stuck-at misses.
ATPG (Automatic Test Pattern Generation) automatically generates input patterns that detect manufacturing faults. Given a scan-inserted netlist, ATPG:
1. Lists all faults — for stuck-at: 2 faults per net (SA0, SA1), ~2M faults for a 1M-net design.
2. For each fault, finds a test: set the stuck node to its opposite value (activate), trace the fault effect through gates to a scan flop or primary output (propagate), and verify the observable value is wrong (observe).
3. Uses algorithms like D-algorithm, PODEM, or FAN — essentially Boolean satisfiability searches through the circuit.
4. Some faults are redundant (no test exists) — ATPG proves this and excludes them.
5. Outputs patterns in STIL/WGL format for ATE.
Tools: Synopsys TetraMAX, Cadence Modus, Siemens Tessent.
Fault coverage = (Detected + Potentially Detected faults) / (Total faults − Redundant faults) × 100%
Industry targets vary by application:
BIST (Built-In Self Test) embeds the test engine on the chip itself — eliminating the need for external ATE for those specific tests. Prefer BIST when:
IDDQ (quiescent supply current) testing measures the chip's DC current while all inputs are held static (no switching). A defect-free CMOS circuit draws near-zero static current because complementary P-channel and N-channel transistors never form a DC path simultaneously in steady state.
Defects that create extra current paths — gate oxide shorts (GOS), resistive bridges between VDD and VSS, parasitic gate-to-drain capacitors — cause IDDQ to be 10× to 1000× higher than normal. These defects often don't create a stuck-at or transition fault but will cause premature field failure due to oxide breakdown or thermal degradation.
IDDQ is particularly valuable for: detecting high-resistance bridges, gate oxide reliability screening, and identifying chips that are structurally "pass" but are reliability risks.
EDT is a test compression technique that reduces ATE test time by 50–200× without significantly reducing fault coverage. Instead of shifting full test patterns directly into scan chains, EDT adds two on-chip modules:
Decompressor: Expands a small number of ATE channels (e.g., 8 channels) into hundreds of scan chains simultaneously using XOR logic. A single ATE shift cycle fills many chains in parallel.
Compactor: At the scan output, XOR-compresses responses from hundreds of chains into a few ATE channels for observation.
Result: ATE only needs to handle 8 channels instead of 800, so the same number of scan chains can be tested in 1/100th the time. Test cost per chip drops proportionally. EDT is standard on all advanced chips — without it, test time at 7nm would be economically prohibitive.
When a chip rolls off the production line, two fundamental questions must be answered before it can be shipped to a customer. The first is physical: was this chip built correctly? The fabrication process, despite its precision, introduces defects — a stray particle on a photomask, a slightly misaligned via, a marginal implant dose — that can make a wire permanently stuck at one logic level, or create a short between two adjacent metal lines. Structural testing exists to catch these manufacturing defects with mathematical certainty, using fault models that abstract physical reality into logical behaviour.
The second question is behavioural: does this chip do what the designer intended? A chip can be manufactured perfectly — every wire intact, every gate functioning — and still be wrong if the RTL had a bug. A FIFO that fills to 255 entries instead of 256 before asserting full. An AXI slave that holds READY low for one cycle too long under back-pressure. A divider that returns the correct quotient but the wrong remainder when the dividend is zero. Functional testing catches these design errors through application-realistic stimuli that structural patterns would never generate.
Neither test type subsumes the other. Structural tests are fast, automatic, and mathematically rigorous about coverage of physical defects — but they are deliberately ignorant of what the chip is supposed to compute. Functional tests are specification-aware and system-realistic — but they cover only the scenarios a human thought to test. Together they form the complete quality gate between the fab and the customer.
In modern SoC design, DFT engineers work alongside RTL designers from the very first design stage — not as an afterthought. Scan insertion, BIST engine placement, and testability analysis happen concurrently with functional design, because design choices that improve RTL elegance often hurt testability, and the cost of low fault coverage at ATE is paid in every chip that reaches a customer with a latent defect.